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LM75BIMMX-3 Datasheet(PDF) 7 Page - Texas Instruments |
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LM75BIMMX-3 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 31 page LM75B, LM75C www.ti.com SNIS153D – JULY 2009 – REVISED OCTOBER 2015 6.7 I 2C Digital Switching Characteristics Unless otherwise noted, these specifications apply for VS = 5 Vdc for LM75BIM-5, LM75BIMM-5, LM75CIM-5, and LM75CIMM-5; and +VS = 3.3 Vdc for LM75BIM-3, LM75BIMM-3, LM75CIM-3, and LM75CIMM-3, CL (load capacitance) on output lines = 80 pF unless otherwise specified. TA = TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN(1)(2) TYP(3) MAX(1)(2) UNIT t1 SCL (Clock) Period, See Figure 1 –55°C ≤ TA ≤ 125°C 2.5 µs t2 Data in Set-Up Time to SCL High, See Figure 1 –55°C ≤ TA ≤ 125°C 100 ns t3 Data Out Stable after SCL Low, See Figure 1 –55°C ≤ TA ≤ 125°C 0 ns t4 SDA Low Set-Up Time to SCL Low (Start Condition), ns –55°C ≤ TA ≤ 125°C 100 See Figure 1 t5 SDA High Hold Time after SCL High (Stop Condition), ns –55°C ≤ TA ≤ 125°C 100 See Figure 1 LM75B –55°C ≤ TA ≤ 125°C 75 325 ms tTIMEOUT SDA Time Low for Reset of Serial Interface(4) Not LM75C Applicable (1) Limits are specified to AOQL (Average Outgoing Quality Level). (2) Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when the SCL and SDA edge rates are similar. (3) Typicals are at TA = 25°C and represent most likely parametric norm. (4) Holding the SDA line low for a time greater than tTIMEOUT will cause the LM75B to reset SDA to the IDLE state of the serial bus communication (SDA set High). Figure 1. Timing Diagram Figure 2. Temperature-to-Digital Transfer Function (Non-Linear Scale for Clarity) Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM75B LM75C |
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