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MPC8266ACZU Datasheet(PDF) 2 Page - Motorola, Inc |
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MPC8266ACZU Datasheet(HTML) 2 Page - Motorola, Inc |
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2 / 48 page  2 MPC826xA (HiP4) Family Hardware Specifications MOTOROLA Features Figure 1 shows the block diagram for the MPC826, the HiP4 superset device. Shaded portions indicate functionality that is not available on all devices; refer to the notes. Figure 1. MPC8266 Block Diagram 1.1 Features The major features of the MPC826xA family are as follows: • Dual-issue integer core — A core version of the EC603e microprocessor — System core microprocessor supporting frequencies of 150–300 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU) — Common on-chip processor (COP) test interface 16 Kbytes G2 Core I-Cache I-MMU 16 Kbytes D-Cache D-MMU Communication Processor Module (CPM) Timers Parallel I/O Baud Rate Generators 32 Kbytes 32-bit RISC Microcontroller and Program ROM Serial DMAs 4 Virtual IDMAs 60x-to-PCI Bridge2,3 Bridge Memory Controller Clock Counter System Functions System Interface Unit (SIU) Local Bus 32 bits, up to 83 MHz PCI Bus2,3 32 bits, up to 66 MHz or MCC1 4 MCC2 FCC1 FCC2 FCC3 4 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Serial Interface 3 MII 2 UTOPIA Ports Ports6 60x Bus Microcode IMA1,3 Dual-Port RAM Interrupt Controller Time Slot Assigner TC Layer Hardware1,3 8 TDM Ports5 Non-Multiplexed I/O 60x-to-Local Bus Interface Unit Notes: 1 MPC8264 2 MPC8265 3 MPC8266 4 Not on MPC8255 5 4 TDM ports on the MPC8255 6 2 MII ports on the MPC8255 |
Similar Part No. - MPC8266ACZU |
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Similar Description - MPC8266ACZU |
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