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NOIP1SN010KA-GDI Datasheet(PDF) 5 Page - ON Semiconductor

Part # NOIP1SN010KA-GDI
Description  Global Shutter CMOS Image Sensors
Download  87 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NOIP1SN010KA-GDI Datasheet(HTML) 5 Page - ON Semiconductor

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NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
www.onsemi.com
5
Table 5. ELECTRICAL SPECIFICATIONS
Boldface Limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C (Notes 6, 7, 8 and 9)
Parameter
Units
Max
Typ
Min
Description
vdd_calib
Pixel calibration supply
4.2
V
gnd_calib
Pixel calibration ground. Not connected to substrate
0
V
vdd_sel
Pixel select supply
4.2
V
gnd_sel
Pixel select ground. Not connected to substrate.
0
0
0
V
vdd_casc
Cascode supply
1.0
V
vref_colmux [9]
Column multiplexer reference supply
1.0
V
gnd_colbias
Column biasing ground. Dedicated ground signal for pixel biasing.
Connected to substrate
0
V
gnd_colpc
Column precharge ground. Dedicated ground signal for pixel biasing.
Not connected to substrate
0
V
Ptot
Total power consumption
4600
mW
Popt
Power consumption at lower pixel rates
Configurable
I/O - LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling - 32 data channels, 1 synchronization channel
720
Mbps
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
360
MHz
Vicm
LVDS input common mode level
0.3
1.25
2.2
V
Tccsk
Channel to channel skew (training pattern allows per-channel skew
correction)
50
ps
LVDS Electrical/Interface
fin
Input clock rate
360
MHz
tidc
Input clock duty cycle
45
50
55
%
tj
Input clock jitter
20
ps
fspi
SPI clock rate
10
MHz
ratspi
10-bit (32 LVDS channels): ratio: fin/fspi
30
10-bit (16 LVDS channels): ratio: fin/fspi
60
10-bit (8 LVDS channels): ratio: fin/fspi
120
10-bit (4 LVDS channels): ratio: fin/fspi
240
6. All parameters are characterized for DC conditions after thermal equilibrium is established.
7. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance
circuit.
8. Minimum and maximum limits are guaranteed through test and design.
9. Vref_colmux supply should be able to source and sink current


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