Electronic Components Datasheet Search |
|
BELASIGNA200 Datasheet(PDF) 2 Page - ON Semiconductor |
|
BELASIGNA200 Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 43 page BelaSigna 200 2.0 Key Features 2.1 System • 16-bit programmable fixed-point DSP core • Configurable WOLA filterbank coprocessor optimized for filterbank calculations • 12-Kword program memory (PRAM) • Two 4-Kword data memories (XRAM and YRAM) • Two 384-word dual-port FIFO memories • Two 128-word dual-port 18-bit memories dedicated to WOLA output results • 576-word memory dedicated to WOLA gain values, WOLA windows and other configuration data • Internal oscillator • Operating voltage of 1.8V nominal • Ultra-low power: less than 1mW @ 1.28MHz system clock frequency, 1.8V nominal operating voltage, both processors running • Available in a QFN package; other packages available upon request 2.2 RCore DSP • Dual-Harvard architecture, 16-bit programmable fixed-point DSP with three execution units • Single-cycle multiply-accumulate (MAC) with 40-bit accumulator • Highly parallel instruction set with powerful addressing modes • Flexible address generation (including modulo addressing) for accessing program memory and data memories, plus control and configuration registers • Separate system and user stacks with dedicated stack pointers • Fast normalization and de-normalization operations optimized for signal level calculation and block-floating point calculations • Supports time-domain pre- and post-processing of input data stream and frequency-domain processing of WOLA output • Master processor for entire system 2.3 WOLA Filterbank Coprocessor • Mono and stereo time-frequency transforms providing real or complex data results • Standard library of overlap-add (OLA) and WOLA filterbank configurations o Configurable number of frequency bands o Configurable number of frequency bands o Configurable oversampling and decimation factors o Configurable windows • Low group delay (< 4ms for 16 bands possible) • Fast real and complex gain application for magnitude and phase processing • Block floating-point calculations (4-bit exponent, 18-bit mantissa) to achieve high fidelity • Maximum digital gain of 90dB possible • High-fidelity time-frequency domain processing • Low-overhead interaction with the RCore through shared memories, control registers and interrupts 2.4 Input Output Processor (IOP) • Block-based DMA for all audio data provides automatic management of input and output FIFOs that reduces processor overhead • Mono (one in, one out), simple stereo (two in, one out), full stereo (two in, two out) and digital mixed (two in, one out) operating modes • Interacts with the RCore through interrupts and shared memories • Normal and smart FIFO audio data accessing schemes available Rev. 16 | Page 2 of 43 | www.onsemi.com |
Similar Part No. - BELASIGNA200 |
|
Similar Description - BELASIGNA200 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |