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100315 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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100315 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page 100315 Low-Skew Quad Clock Driver General Description The 100315 contains four low skew differential drivers, de- signed for generation of multiple, minimum skew differential clocks from a single differential input. This device also has the capability to select a secondary single-ended clock source for use in lower frequency system level testing. The 100315 is a 300 Series redesign of the 100115 clock driver. Features n Low output to output skew ( ≤50 ps) n Differential inputs and outputs n Secondary clock available for system level testing n 2000V ESD protection n Voltage compensated operating range: −4.2V to −5.7V n Standard Microcircuit Drawing (SMD) 5962-9469601 Logic Diagram Connection Diagram Pin Names Description CLKIN, CLKIN Differential Clock Inputs CLK 1–4, CLK1–4 Differential Clock Outputs TCLK Test Clock Input (Note 1) CLKSEL Clock Input Select (Note 1) Note 1: TCLK and CLKSEL are single-ended inputs, with internal 50 k Ω pull- down resistors. Truth Table CLKSEL CLKIN CLKIN TCLK CLK N CLK N LL H X L H LH L X H L HX X L L H HX X H H L L = Low Voltage Level H = High Voltage Level X = Don’t Care DS100319-1 Flatpak DS100319-2 August 1998 © 1998 National Semiconductor Corporation DS100319 www.national.com |
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