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LV8907UW Datasheet(PDF) 5 Page - ON Semiconductor |
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LV8907UW Datasheet(HTML) 5 Page - ON Semiconductor |
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5 / 45 page  LV8907UW www.onsemi.com 5 PIN DESCRIPTION Pin Name Pin No Description VCC 1 5V or 3.3V regulator output pin. (Selected by internal register setting) Power supply for microcontroller. Connect capacitor to AGND for stability. RXD 2 Open drain logic level output of LIN_PWMIN received data. Use pullup to a voltage less than or equal to VS. TXD 3 Logic level input of transmit data for LIN_PWMIN. PWMIN 4 Digital level PWM input pin for direct drive or speed selection. See page 18 for details. Input polarity can be programmed for either active high or active low. AGND 5 Analog GND pin. NC 6, 14, 16,18, 21, 23 No Connections CSB 7 Active low SPI interface chip selection pin. See page 23 for SPI timing details. SCLK 8 SPI interface clock input pin. See page 23 for SPI timing details. SI 9 Active high SPI interface serial data input pin. See page 23 for SPI timing details. SO 10 Open drain SPI interface serial data output pin. See page 23 for SPI timing details. FG 11 Open drain back-EMF transition output pin. The frequency is selectable via register settings. DIAG 12 Programmable open drain diagnostic output. LGND 13 LIN Block GND pin. LIN_ PWMIN 15 LIN transceiver input/output. Register selectable as PWM input with a VVS/2 threshold. TEST 17 Factory test pin. Connect to GND. TH 19 Thermistor input pin for FET temperature detection. If the input voltage is below the threshold voltage, an error is triggered. The error threshold is programmable. To disable tie to V3RO. RFSENS 20 Shunt resistance reference pin. Connect this pin to the GND side of the Shunt resistor with Kelvin leads. RF 22 Output current detect pin. Connect this pin to output side of shunt resistor with Kelvin leads. The maximum peak motor current is limited to the value calculated by IOUT=100mV/RF. COM 24 COM input pin. Connect this pin to the motor neutral point. This point may be derived from a resistive network with 1k resistors to the phases. SUL SVL SWL 33 29 25 Current return path for low-side gate drive. Short circuit shutoff level is measured between this pin and its corresponding phase pin. UL VL WL 34 30 26 Gate driver output pin for the low-side Nch Power FET. Use gate resistors for wave-shaping. UOUT VOUT WOUT 35 31 27 Current return path for high-side gate drive and reference for short circuit shut-off. UH VH WH 36 32 28 Gate driver output pin for the high-side Nch Power FET. Use gate resistors for wave-shaping. PGND 37 GND pin for the charge pump output drives. VGL 38 Power supply pin for low-side gate drive. Connect decoupling capacitor between this pin and GND. CHP 39 Power supply pin for high-side gate drive. Connect decoupling capacitor between this pin and VS. CP1N 40 Charge transfer pin of the Charge pump (1N). Connect capacitor to CP1P-CP1N. CP1P 41 Charge transfer pin of the Charge pump (1P). Connect capacitor to CP1P-CP1N. CP2P 42 Charge transfer pin of the Charge pump (2P). Connect capacitor to CP2P-CP2N. CP2N 43 Charge transfer pin of the Charge pump (2N). Connect capacitor to CP2P-CP2N. VS 44 Power supply pin. WAKE 45 WAKE pin. “H” = Operating mode, “L” or “Open” = Sleep mode. |
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