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CM2009-00QR Datasheet(PDF) 2 Page - ON Semiconductor |
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CM2009-00QR Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 6 page CM2009 http://onsemi.com 2 SIMPLIFIED ELECTRICAL SCHEMATIC VIDEO_1 VIDEO_2 VIDEO_3 VCC_VIDEO GND SYNC_OUT2 GND VCC_DDC VCC_SYNC SYNC_OUT1 SYNC_IN2 SYNC_IN1 DDC_IN2 DDC_IN1 RT 3 4 5 6 10 11 13 15 1 8 2 14 16 DDC_OUT2 DDC_OUT1 12 9 BYP RT 7 PACKAGE / PINOUT DIAGRAM Top View 16 Pin QSOP VCC_SYNC 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC BYP SYNC_IN2 SYNC_OUT1 SYNC_OUT2 SYNC_IN1 DDC_OUT2 DDC_IN2 DDC_IN1 DDC_OUT1 VCC_VIDEO Table 1. PIN DESCRIPTIONS Lead(s) Name Description 1 VCC_SYNC This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD protection circuits. 2 VCC_VIDEO This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits. 3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 4 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 5 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 6 GND Ground reference supply pin. 7 VCC_DDC This is an isolated supply input for the DDC_1 and DDC_2 level−shifting N−FET gates. 8 BYP This input is used to connect an external 0.2 mF bypass capacitor to the DDC circuits, resulting in an increased ESD withstand voltage rating for these circuits (±8 kV with vs. ±4 kV without). 9 DDC_OUT1 DDC signal output. Connects to the video connector side of one of the sync lines. 10 DDC_IN1 DDC signal input. Connects to the VGA controller side of one of the sync lines. |
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