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PCS3P623Z05A Datasheet(PDF) 2 Page - ON Semiconductor

Part # PCS3P623Z05A
Description  Peak EMI Reduction IC
Download  13 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

PCS3P623Z05A Datasheet(HTML) 2 Page - ON Semiconductor

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PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B
http://onsemi.com
2
Figure 1. General Block Diagrams
PLL
CLKIN
DLY_CTRL
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
PCS3P623Z05A/B
S2
S1
Select
Input
Decoding
PLL
CLKIN
MUX
DLY_CTRL
CLKOUTA1
CLKOUTA2
CLKOUTA3
CLKOUTA4
CLKOUTB1
CLKOUTB2
CLKOUTB3
CLKOUTB4
PCS3P623Z09A/B
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the edge
rates also get faster. Analysis shows that a square wave is
composed of fundamental frequency and harmonics. The
fundamental frequency and harmonics generate the energy
peaks that become the source of EMI. Regulatory agencies
test electronic equipment by measuring the amount of peak
energy radiated from the equipment. In fact, the peak level
allowed decreases as the frequency increases. The standard
methods of reducing EMI are to use shielding, filtering,
multi−layer PCBs, etc. These methods are expensive.
Spread spectrum clocking reduces the peak energy by
reducing the Q factor of the clock. This is done by slowly
modulating the clock frequency. The PCS3P623Z05/09 uses
the center modulation spread spectrum technique in which
the modulated output frequency varies above and below the
reference frequency with a specified modulation rate. With
center modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation.
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output. Since the DLY_CTRL pin
is the internal feedback to the PLL, its relative loading can
adjust the input−output delay.
For applications requiring zero input−output delay, all
outputs, including DLY_CTRL, must be equally loaded.
Even if DLY_CTRL is not used, it must have a capacitive
load equal to that on other outputs, for obtaining zero
input−output delay.
Timing−Safe Technology
Timing−Safe technology is the ability to modulate a clock
source with Spread Spectrum technology and maintain
synchronization with any associated data path.


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