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Z8L189 Datasheet(PDF) 9 Page - Zilog, Inc. |
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Z8L189 Datasheet(HTML) 9 Page - Zilog, Inc. |
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9 / 107 page  9 PRELIMINARY Z80189/Z8L189 GENERAL-PURPOSE EMBEDDED CONTROLLERS DS971890301 Zilog Figure 8. DMA Control Signals Ø 45 46 45 45 47 17 48 18 CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi) T1 T2 Tw T3 T1 [3] [4] [2] [1] /DREQi (At level sense) /DREQi (At edge sence) /TENDi ST DMA Control Signals [ 1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3. [2] tDRQS and tDRQH are specified for the rising edge of clock. [3] DMA cycle starts. [4] CPU cycle starts. Figure 7. CPU Timing 0 Address /IROQ T1 T2 TW T3 T1 13 25 9 /RD /WR T2 TW T3 I/O Read Cycle I/O Write Cycle 28 29 28 29 22 TIMING DIAGRAMS (Continued) |
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