Ver. DEM

MN103SJ7/N0/N1/N2/N4/N5/N6 Series

2

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Features

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CPU core

MN103S core

4 GB of address space (for instructions / data)

LOAD/STORE architecture with 5-stage pipeline

46 basic instructions + 8 extension instructions

6 addressing modes

Instruction set of 1 byte in word length

Extension arithmetic unit incorporated (high-speed multiply instruction, high-speed division instruction etc.)

Machine cycle: 16.7 ns (oscillation frequency: 10 MHz, 6 multiplying)

Operation mode: NORMAL mode, SELLP mode, HALT mode, STOP mode

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Oscillation Circuit

External oscillation (crystal/ ceramic)

Clock multiply circuit Oscillation clock can be multiplied by from 3 to 12

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Internal memory

ROM: 32 K/64 K/128 K bytes

RAM: 2 K/4 K/6 K/8 K bytes

The ROM/RAM size is different in each product.

Please refer to [ Product Summary] for details.

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DMA Controller

Number of channels:1 channel

Startup sources:

15 sources (MN103SFN0/N4 series)

20 sources (MN103SFN1/N5 series)

22 sources (MN103SFN2/N6 series)

(External interrupts: Max 12 sources, Serial Interface: Max 9 sources, Software start: 1 source)

Transfer modes:

3 modes (One word transfer, Burst transfer, Intermittent transfer)

*: There is not the function in the MN103SFJ7A.

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Interrupts

Non-maskable interrupts

Watchdog timer overflow interrupts

System error interrupts

Fail safe function interrupts

Internal interrupts (Level interrupt)

MN103SFJ7A

: 23 interrupts

MN103SFN0/N4 series: 29 interrupts

MN103SFN1/N5 series: 42 interrupts

MN103SFN2/N6 series: 48 interrupts

<Timer Interrupts>

Timer 0 underflow interrupt

Timer 1 underflow interrupt

Timer 2 underflow interrupt

Timer 3 underflow interrupt

Timer 4 underflow interrupt

Timer 5 underflow interrupt

Timer 6 underflow interrupt

Timer 7 underflow interrupt

Timer 8 underflow interrupt

Timer 9 underflow interrupt

Timer 10 underflow interrupt

Timer 11 underflow interrupt

Timer 16 overflow/underflow interrupt

Timer 16 compare/capture A interrupt