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LMH6601-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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LMH6601-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 40 page  LMH6601, LMH6601-Q1 www.ti.com SNOSAK9F – JUNE 2006 – REVISED JUNE 2015 Electrical Characteristics, 3.3 V (continued) Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V +, V OUT = VS/2, RL = 150 Ω to V − unless otherwise specified.(1) PARAMETER TEST CONDITIONS MIN(2) TYP(2) MAX(2) UNIT TIME DOMAIN RESPONSE OS Overshoot 0.25-V Step 10% CL Capacitor Load Tolerance AV = −1, 10% Overshoot, 82 Ω in Series 50 pF DISTORTION and NOISE PERFORMANCE HD2 2 VPP, 10 MHz −61 Harmonic Distortion (2nd) dBc 2 VPP, 10 MHz HD2_1 −79 RL = 1 kΩ to VS/2 HD3 2 VPP, 10 MHz −53 Harmonic Distortion (3rd) dBc 2 VPP, 10 MHz HD3_2 −69 RL = 1 kΩ to VS/2 2 VPP, 10 MHz THD Total Harmonic Distortion −66 dBc RL = 1 kΩ to VS/2 VN1 >10 MHz 7 Input Voltage Noise nV/ √Hz VN2 1 MHz 10 IN Input Current Noise >1 MHz 50 fA/ √Hz STATIC, DC PERFORMANCE ±1 ±2.6 VIO Input Offset Voltage mV At temperature extremes ±5.5 DVIO Input Offset Voltage Average Drift See (3) −4.5 μV/°C IB Input Bias Current See (4) 5 50 pA IOS Input Offset Current See (4) 2 25 pA RIN Input Resistance 0 V ≤ VIN ≤ 1.8 V 15 T Ω CIN Input Capacitance 1.4 pF DC 61 80 Positive Power Supply Rejection +PSRR dB Ratio At temperature extremes 51 DC 57 72 Negative Power Supply Rejection −PSRR dB Ratio At temperature extremes 52 DC 58 73 CMRR Common-Mode Rejection Ratio dB At temperature extremes 55 CMRR > 50 dB (At temperature CMVR Input Voltage V− – 0.20 V+ – 1.5 V extremes) 9.2 11 Normal Operation mA At temperature VOUT = VS/2 ICC Supply Current 13 extremes Shutdown: SD tied to ≤ 0.33 V(5) 100 nA –210 –190 VOH1 RL = 150 Ω to V – At temperature –360 extremes Output High Voltage VOH2 RL = 75 Ω to VS/2 –190 mV (Relative to V+) –50 –10 VOH3 RL = 10 kΩ to V − At temperature –100 extremes (3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. (4) This parameter is ensured by design and/or characterization and is not tested in production. (5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply voltage away from either supply rail. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMH6601 LMH6601-Q1 |
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