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1008CS-681XJLC Datasheet(PDF) 11 Page - Integrated Device Technology |
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1008CS-681XJLC Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 13 page  Intermediate Frequency Digital Variable Gain Amplifier IDTF1200 RevO Page 11 of 13 April, 2011 DATASHEET PIN DESCRIPTIONS Pin # Pin Name Function 1 GND 2 VCC_ATTN Attenuator Power Supply 3 ATTN_IN+ Attenuator_0 Differential Input P 4 ATTN_IN- Attenuator_0 Differential Input M 5 Ground Untested - SPI Chip Select Input 6 Ground Untested - SPI Data Input 7 Ground Untested - SPI Clock Input 8 GC6 Parallel Gain Control Input – MSB (16 dB step) 9 GC5 Parallel Gain Control Input 10 GC4 Parallel Gain Control Input 11 GC3 Parallel Gain Control Input 12 GC2 Parallel Gain Control Input 13 GC1 Parallel Gain Control Input 14 GC0 Parallel Gain Control Input – LSB (0.25 dB step) 15 VCC_DIG Digital Circuit Power Supply 16 DIG_GND Connect directly to Ground 17 VMODE Untested – SPI Enable Connect to PCB GND for normal parallel operation 18 AMP_OUT+ Amplifier Differential Output P 19 AMP_OUT- Amplifier Differential Output M 20 STBY Amplifier Power Down. Ground for Normal operation 21 ISET Current Setting Resistor. Connect recommended value (2.87K) to ground. Use 1% tolerance 22 VCC_Amp_Bias Amplifier and Bias Circuit Power Supply 23 Bias_Amp Amplifier Bias External Pin for Decoupling Capacitor 24 AMP_IN+ Amplifier Differential Input P 25 E_Amp Amplifier Common Emitter 26 AMP_IN- Amplifier Differential Input M 27 ATTN_OUT- Attenuator_0 Differential Output M 28 ATTN_OUT+ Attenuator_0 Differential Output P Exposed Paddle |
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