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ERJ-2RKF2801X Datasheet(PDF) 6 Page - Integrated Device Technology |
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ERJ-2RKF2801X Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 28 page DPD Demodulator for PA Linearization 550MHz to 1150MHz IDT Zero-Distortion TM, Glitch-FreeTM DPD Receiver 6 Rev4 January 2014 F1300 DATASHEET IDTF1320NBGI Datasheet ARY DATASHEET POWER-ON SEQUENCE The power-on sequence ensures F1320 works in default mode once powered on. If the F1320 is programmed after applying DC power, the following power-on sequence is not needed. The power-on sequence should be: 1. CSb & SW_LATCH must be set low at power-on 2. Once powered on, first set SW_LATCH high, then set CSb high 3. Proceed with normal programming. The default state after using power-on sequence: Maximum attenuation RF_INX, LO_INA selected Normal operation (not Standby Mode) SERIAL PROGRAMMING The device is programmed via the serial port by asserting Chip Select (CSb). Note: Most-Significant-Bit first, where the Address Word is the Most-Significant-Byte. Serial mode timing diagram high level: Address Word A7 – A0 Data Word D7 – D0 D5 D4 D0 D3 D1 D2 16 dB RFSW CLK DATA Data Word Latched into Register LSB CS RSV RSV RSV RSV RSV RSV RSV 0 0 ENb 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 dB 4 dB 2 dB 1 dB 0.5 dB MSB 1 = RFY 0 = RFX 1 = OFF 0 = ON Polarity: 1 = ATTN ON 0 = ATTN OFF SW_Latch Clock in MSB first Increasing time LOSW D6 D7 A5 A4 A0 A3 A1 A2 A6 A7 1 = LOB 0 = LOA |
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