9

FN8113.2

June 30, 2008

performed. When the R/W bit is a one, then a read

operation is selected. A zero selects a write operation.

Refer to Figure 9.

• After loading the entire slave address byte from the SDA

bus, the device compares the input slave byte data to the

proper slave byte. Upon a correct compare, the device

outputs an acknowledge on the SDA line.

Write Control Register

To write to the control register, the device requires the slave

address byte and a byte address. This gives the master

access to register. After receipt of the address byte, the

device responds with an acknowledge, and awaits the data.

After receiving the 8 bits of the data byte, the device again

responds with an acknowledge. The master then terminates

the transfer by generating a stop condition, at which time the

device begins the internal write cycle to the nonvolatile memory.

During this internal write cycle, the device inputs are disabled,

so the device will not respond to any requests from the master.

If WP is HIGH, the control register cannot be changed. A write

to the control register will suppress the acknowledge bit and no

data in the control register will change. With WP low, a second

byte written to the control register terminates the operation and

no write occurs.

Stops and Write Modes

Stop conditions that terminate write operations must be sent by

the master after sending 1 full data byte plus the subsequent

ACK signal. If a stop is issued in the middle of a data byte, or

before 1 full data byte plus its associated ACK is sent, then the

device will reset itself without performing the write.

Serial Read Operations

The read operation allows the master to access the control

slave address byte with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

issues the start condition and the slave address byte,

receives an acknowledge, then issues the byte address.

After acknowledging receipt of the byte address, the master

immediately issues another start condition and the slave

address byte with the R/W bit set to one. This is followed by

an acknowledge from the device and then by the eight bit

control register. The master terminates the read operation by

not responding with an acknowledge and then issuing a stop

condition. Refer to Figure 10 for the address, acknowledge,

and data transfer sequences.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• The WEL bit is set to ‘0’. In this state it is not possible to

write to the device.

• SDA pin is the input mode.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

• The WEL bit must be set to allow a write operation.

• The proper clock count and bit sequence is required prior

to the stop bit in order to start a nonvolatile write cycle.

• A three step sequence is required before writing into the

control register to change watchdog timer or block lock

settings.

• The WP pin, when held HIGH, prevents all writes to the

control register.

voltage.

• Command to change the control register are terminated if

in-progress when RESET/RESET go active.

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

SLAVE

ADDRESS

BYTE

ADDRESS

A

C

K

A

C

K

S

T

A

R

T

S

T

O

P

SLAVE

ADDRESS

DATA

A

C

K

S

T

A

R

T

SDA BUS

SIGNALS

FROM THE

SLAVE

SIGNALS

FROM THE

MASTER

0

1

0

0

1

1

0

11

1

1

1

1

1

1

11

1

0

0

1

1

0

1

FIGURE 10. CONTROL REGISTER READ SEQUENCE

X4003, X4005