AX88140A

PRELIMINARY

ASIX ELECTRONICS CORPORATION

2

CONTENTS

1.0 INTRODUCTION ................................................................................................................................................ 6

2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11

3.0 CONFIGURATION OPERATION .................................................................................................................. 17

3.2.1 Configuration ID Register (CSID)............................................................................................................ 18

3.2.2 Command and Status Configuration Register (CSCS)............................................................................... 18

3.2.3 Configuration Revision Register (CSRV).................................................................................................. 18

3.2.4 Configuration Latency Timer Register (CSLT)......................................................................................... 18

3.2.5 Configuration Base I/O Address Register (CBIO).................................................................................... 19

3.2.6 Configuration Base Memory Address Register (CBMA) .......................................................................... 19

3.2.7 Expansion ROM Base Address Register (CBER)...................................................................................... 19

3.2.8 Configuration Interrupt Register (CSIT) .................................................................................................. 19

4.0 REGISTERS OPERATION .............................................................................................................................. 20

4.2.1 Bus Mode Register (REG0)........................................................................................................................ 21

4.2.2 Transmit Poll Demand (REG1)................................................................................................................. 21

4.2.3 Receive Poll Demand (REG2)................................................................................................................... 22

4.2.4 Receive List Base Address (REG3) ........................................................................................................... 22

4.2.5 Transmit List Base Address (REG4) ......................................................................................................... 22

4.2.6 Status Register (REG5) ............................................................................................................................. 23

4.2.7 Operation Mode Register (REG6) ............................................................................................................ 24

4.2.8 Interrupt Enable Register (REG7) ............................................................................................................ 26

4.2.9 Missed Frame and Overflow Counter (REG8) ........................................................................................ 26

4.2.10 Serial ROM and MII Management Register (REG9).............................................................................. 27

4.2.11 General-Purpose Timer (REG11)........................................................................................................... 27

4.2.12 General-Purpose Port Register (REG12) ............................................................................................... 28

4.2.13 Filtering Index (REG13) ......................................................................................................................... 28

4.2.14 Filtering data (REG14)........................................................................................................................... 28

5.0 HOST COMMUNICATION.............................................................................................................................. 30

5.2.1 Receive Descriptor 0 (RDES0) .................................................................................................................. 31

5.2.2 Receive Descriptor 1 (RDES1) .................................................................................................................. 32

5.2.3 Receive Descriptor 2 (RDES2) .................................................................................................................. 32

5.2.4 Receive Descriptor 3 (RDES3) .................................................................................................................. 32

5.3.1 Transmit Descriptor 0 (TDES0)................................................................................................................. 33

5.3.2 Transmit Descriptor 1 (TDES1)................................................................................................................. 34

5.3.3 Transmit Descriptor 2 (TDES2)................................................................................................................. 34

5.3.4 Transmit Descriptor 3 (TDES3)................................................................................................................. 34