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PCA9564 Datasheet(PDF) 3 Page - NXP Semiconductors |
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PCA9564 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 31 page  Philips Semiconductors Product data PCA9564 Parallel bus to I2C-bus controller 2003 Apr 02 3 PIN CONFIGURATION — SO, TSSOP 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 D0 D1 D2 D3 D4 D5 D6 D7 DNU VSS VDD SDA SCL RESET INT A1 A0 RD CE WR 10 su01485 PIN CONFIGURATION — HVQFN 15 14 13 12 11 1 2 3 4 5 su01665 TOP VIEW D2 D3 D4 D5 D6 D7 DNU GND (VSS) WR RD CE INT RESET A0 A1 SCL SDA VDD D0 D1 PIN CONFIGURATION PIN NUMBER SO, TSSOP HVQFN SYMBOL PIN TYPE NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 8 1, 2, 3, 4, 5, 18, 19, 20 D0-D7 I/O Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the controller and the CPU. D0 is the least significant bit. 9 6 DNU Do not use: must be left floating (pulled low internally) 10 7 VSS Pwr Ground 11 8 WR I Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. 12 9 RD I Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RD. 13 10 CE I Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the controller are enabled on D0-D7 as controlled by the WR, RD and A0-A1 inputs. When HIGH, places the D0-D7 lines in the 3-State condition. 14, 15 11, 12 A0, A1 I Address Inputs: Selects the controller internal registers and ports for read/write operations. 16 13 INT O Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device. 17 14 RESET I Reset: A LOW level clears internal registers resets the I2C state machine. 18 15 SCL I/O I2C-bus serial clock input/output (open-drain). 19 16 SDA I/O I2C-bus serial data input/output (open-drain). 20 17 VDD Pwr Power Supply: 2.3 to 3.6 V |
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