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CXK77P36E160GB-43E Datasheet(PDF) 3 Page - Sony Corporation |
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CXK77P36E160GB-43E Datasheet(HTML) 3 Page - Sony Corporation |
3 / 25 page SONY® CXK77P36E160GB / CXK77P18E160GB Preliminary 16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1 3 / 25 March 2, 2001 1M x 18 Pin Assignment (Top View) Notes: 1a. Pad Location 4T is a true no-connect. However, it is defined as an SA address input in x36 LW SRAMs. 1b. Pad Locations 2D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, and 6P are true no-connects. However, they are defined as DQ data inputs / outputs in x36 LW SRAMs. 2. Pad Location 6U must be left unconnected. It is used by Sony for internal test purposes. 3. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied “high” in this device. 4. Pad Location 5R is defined as an M2 mode pin in this device. It must be tied “high” or “low”. When M2 is tied “high”, this device functions as a conventional 16Mb R-L SRAM. When M2 is tied “low”, this device functions as an Error-Correcting 8Mb R-L SRAM. 5. Pad Location 2B is defined as an SA address input in 16Mb LW SRAMs. However, it functions as a conventional SA address input in this device only when M2 is tied “high”. It is ignored in this device when M2 is tied “low”. 6. Pad Location 4F is defined as a G output enable input in LW SRAMs. However, it must be tied “low” in this device. 1 2 3 4 5 6 7 A VDDQ SA SA NC SA SA VDDQ B NC SA (5) SA NC SA SA NC C NC SA SA VDD SA SA NC D DQb NC (1b) VSS ZQ VSS DQa NC (1b) E NC (1b) DQb VSS SS VSS NC (1b) DQa F VDDQ NC (1b) VSS G (6) VSS DQ6a VDDQ G NC (1b) DQb SBWb NC VSS NC (1b) DQa H DQb NC (1b) VSS NC VSS DQa NC (1b) J VDDQ VDD VREF VDD VREF VDD VDDQ K NC (1b) DQb VSS K VSS NC (1b) DQa L DQb NC (1b) VSS K SBWa DQa NC (1b) M VDDQ DQb VSS SW VSS NC (1b) VDDQ N DQb NC (1b) VSS SA VSS DQa NC (1b) P NC (1b) DQb VSS SA VSS NC (1b) DQa R NC SA M1 (3) VDD M2 (4) SA NC T NC SA SA NC (1a) SA SA ZZ U VDDQ TMS TDI TCK TDO RSVD (2) VDDQ |
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