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BRCF016GWZ-3 Datasheet(PDF) 3 Page - Rohm |
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BRCF016GWZ-3 Datasheet(HTML) 3 Page - Rohm |
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3 / 28 page  Datasheet 3/25 BRCF016GWZ-3 ©2015 ROHM Co., Ltd. All rights reserved. TSZ22111･15･001 www.rohm.com 23.Sep.2015 Rev.001 TSZ02201-0929AG100010-1-2 AC Characteristics (Unless otherwise specified, Ta=-40℃ to +85℃, Vcc=1.7V to 5.5V) Parameter Symbol Limits 1.7V≦Vcc≦5.5V Unit Min Typ Max Clock Frequency fSCL - - 1000 kHz Data Clock High Period tHIGH 0.3 - - µs Data Clock Low Period tLOW 0.5 - - µs SDA and SCL Rise Time (1) tR - - 0.12 µs SDA and SCL (INPUT)Fall Time (1) tF1 - - 0.12 µs SDA(OUTPUT) Fall Time (1) tF2 - - 0.12 µs Start Condition Hold Time tHD:STA 0.25 - - µs Start Condition Setup Time tSU:STA 0.20 - - µs Input Data Hold Time tHD:DAT 0 - - ns Input Data Setup Time tSU:DAT 50 - - ns Output Data Delay Time tPD 0.05 - 0.45 µs Output Data Hold Time tDH 0.05 - - µs Stop Condition Setup Time tSU:STO 0.25 - - µs Bus Free Time tBUF 0.5 - - µs Write Cycle Time tWR - - 5 ms Noise Spike Width (SDA and SCL) tI - - 0.05 µs (1) Not 100% TESTED. Condition Input Data Level: VIL=0.2×Vcc VIH=0.8×Vcc Input Data Timing Reference Level: 0.3×Vcc/0.7×Vcc Output Data Timing Reference Level: 0.3×Vcc/0.7×Vcc Rise/Fall Time: ≦20ns Serial Input / Output Timing ○ Input Read at the rise edge of SCL ○ Data Output in sync with the fall of SCL Figure 1-(a). Serial Input / Output Timing Figure 1-(b). Start-Stop Bit Timing Figure 1-(c). Write Cycle Timing SCL SDA (input) SDA (output) tR tF tHIGH tSU:DAT tLOW tHD:DAT tDH tPD tBUF 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 70% 70% tSU:STA tHD:STA START CONDITION tSU:STO STOP CONDITION 30% 30% 70% 70% SDA (input) SCL D0 ACK tWR write data (n-th address) START CONDITION STOP CONDITION 70% 70% SCL SDA (input) |
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