SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

6

INA220

SBOS459E – JUNE 2009 – REVISED JANUARY 2016

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Product Folder Links: INA220

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Copyright © 2009–2016, Texas Instruments Incorporated

Electrical Characteristics (continued)

(1) = 1, unless

otherwise noted.

TEST CONDITIONS

INA220A

INA220B

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

DIGITAL INPUTS (SDA as Input, SCL, A0, A1)

Input capacitance

3

3

pF

Leakage input current

0

0.1

1

0.1

1

μA

6

6

V

–0.3

–0.3

V

Hysteresis

500

500

mV

OPEN-DRAIN DIGITAL OUTPUTS (SDA)

Logic 0 output level

0.15

0.4

0.15

0.4

V

High-level output leakage current

0.1

1

0.1

1

μA

POWER SUPPLY

Operating supply range

3

5.5

3

5.5

V

Quiescent current

0.7

1

0.7

1

mA

Quiescent current, power-down mode

6

15

6

15

μA

Power-on reset threshold

2

2

V

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not ensured and not

production tested. Condition: A0=A1=0.

7.6 Bus Timing Diagram Definitions

(1)

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

SCL operating frequency

0.001

0.4

0.001

2.56

MHz

Bus free time between STOP and START

condition

1300

160

ns

Hold time after repeated START condition

After this period, the first clock is

generated.

600

160

ns

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

0

900

0

90

ns

Data setup time

100

10

ns

SCL clock LOW period

1300

250

ns

SCL clock HIGH period

600

60

ns

Data fall time

300

150

ns

Clock fall time

300

40

ns

Clock rise time

300

40

ns

Clock rise time for SCLK

≤ 100 kHz

1000

ns

Figure 1. Bus Timing Diagram