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FMT1000 Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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FMT1000 Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 29 page © 2015 Fairchild Semiconductor Corporation www.fairchildsemi.com FMT1000-series • Rev. 1.0 7 1.7 Peripheral Interface Selection The FMT1000-series modules are designed to be used as a peripheral device in embedded systems. The module supports Universal Asynchronous Receiver/Transmitter (UART), inter-integrated circuit (I 2C) and the Serial Peripheral Interface (SPI) protocols. The I 2C and SPI protocols are well suited for communications between integrated circuits with on- board peripherals. The FMT1000-series modules have four modes of peripheral interfacing. Only one mode can be used at a time and is determined by the state of peripheral selection pins PSEL0 and PSEL1 at startup. Table 1 specifies how the PSEL lines select the peripheral interface. Note that the module has internal pull-ups. Not connecting PSEL results in a value of 1, connecting PSEL to a GND results in a value of 0. Examples for communication on embedded systems are available at https://developer.mbed.org/teams/Fairchild- Semiconductor Table 1. Peripheral Interface Selection Interface PSEL0 PSEL1 I 2C 1 1 SPI 0 1 UART Half-Duplex 1 0 UART Full-Duplex 0 0 1.7.1 Peripheral Interface Architecture At its core the module uses the proprietary Xbus protocol. This protocol is available on all interfaces, UART (asynchronous serial port interfaces) and I 2C and SPI buses. The I 2C and SPI buses differ from UART in that they are synchronous and have a master-slave relation in which the slave cannot send data by itself. This makes the Xbus protocol not directly transferable to these buses. For this the MTSSP protocol is introduced that provides a way to exchange standard Xbus protocol messages over the I 2C and SPI buses. Figure 5 shows how MTSSP is fitted in the module's (simplified) communication architecture. The module has generic Input- and Output-Queues for Xbus protocol messages. For I 2C and SPI these messages are translated by the MTSSP layer. For the UART connection these messages are transported as-is. Figure 5. FMT Module Architecture |
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