PCM1753, PCM1754, PCM1755

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SLES092D – APRIL 2010 – REVISED AUGUST 2015

7.5 Electrical Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

24

Bits

DATA FORMAT

Sampling frequency

5

200

kHz

System clock frequency

kHz

DIGITAL INPUT/OUTPUT

Logic family

TTL compatible

Input logic level, high

2

VDC

Input logic level, low

0.8

VDC

Input logic current, high (SCK, BCK, DATA,

10

µA

and LRCK pins)

Input logic current, low (SCK, BCK, DATA,

-10

µA

and LRCK pins)

Input logic current, high (TEST, DEMP,

65

100

µA

MUTE, and FMT pins)

Input logic current, low (TEST, DEMP,

-10

µA

MUTE, and FMT pins)

Output logic level, high (ZEROA pin)

2.4

VDC

Output logic level, low (ZEROA pin)

0.4

VDC

0%

0.01%

THD+N at VOUT = 0 dB

0%

0%

0.65%

THD+N at VOUT = -60 dB

0.80%

0.95%

100

106

Dynamic range

104

dB

102

100

106

Signal-to-noise ratio

104

dB

102

97

103

Channel separation

101

dB

100

Level linearity error

VOUT = -90 dB

±0.5

dB

DC ACCURACY

% of

Gain error

±1

±6

FSR

% of

Gain mismatch, channel-to-channel

±1

±3

FSR

Bipolar zero error

±30

±60

mV

(1)

Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in

the averaging mode.

(2)

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