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PCM1794ADBG4 Datasheet(PDF) 7 Page - Texas Instruments |
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PCM1794ADBG4 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 34 page  PCM1794A www.ti.com SLES117B – AUGUST 2004 – REVISED DECEMBER 2015 Electrical Characteristics (continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Stop band 0.732 fS Pass-band ripple ±0.001 dB Stop-band attenuation Stop band = 0.732 fS –100 dB Delay time 18 / fS s POWER SUPPLY REQUIREMENTS fS = 44.1 kHz 12 15 IDD Digital supply current(4) fS = 96 kHz 23 mA fS = 192 kHz 45 fS = 44.1 kHz 33 40 ICC Analog supply current(4) fS = 96 kHz 35 mA fS = 192 kHz 37 fS = 44.1 kHz 205 250 Power dissipation(4) fS = 96 kHz 250 mW fS = 192 kHz 335 (4) Input is BPZ data. 6.6 Timing Requirements MIN MAX UNIT SYSTEM CLOCK INPUT TIMING (see Figure 1) t(SCY) System-clock pulse-cycle time 13 ns t(SCKH) System-clock pulse duration, HIGH 0.4 × t(SCY) ns t(SCKL) System-clock pulse duration, LOW 0.4 × t(SCY) ns EXTERNAL RESET TIMING (see Figure 2) t(RST) Reset pulse duration, LOW 20 ns AUDIO INTERFACE TIMING (see Figure 3) t(BCY) BCK pulse-cycle time 70 ns t(BCL) BCK pulse duration, LOW 30 ns t(BCH) BCK pulse duration, HIGH 30 ns t(BL) BCK rising edge to LRCK edge 10 ns t(LB) LRCK edge to BCK rising edge 10 ns t(DS) DATA setup time 10 ns t(DH) DATA hold time 10 ns LRCK clock duty 50% ± 2-bit clocks Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: PCM1794A |
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