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Revision 1.0

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AS8202B

Datasheet - Pin Assignm ents

A[11:0]

48-42, 39-35

TTL Input

Host Interface (CNI) Address Bus

2

D[15:0]

69-62, 58-51

TTL input/output with tristate Host Interface (CNI) Data Bus, tristate

CEB

76

TTL Input with internal weak

pull-up

Host Interface (CNI) chip enable, active low

OEB

77

Host interface (CNI) output enable, active low

WEB

78

Host interface (CNI) write enable, active low

READYB

79

TTL output with internal weak

pull-up at tristate

Host interface (CNI) transfer finish signal, active low, open

drain

3

INTB

28

Host interface (CNI) time signal (interrupt), active low, open

drain

LED[2:0]

33-31

TTL output with internal weak

pull-down at tristate

Configurable generic output port

NC

1, 27, 40

Not connected, leave open

1. This pin selects a clock multiplier of 1. This is the only supported operation mode.

2. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-granular address bus, remem-

ber that A[11:0] of the AS8202B device has to be connected to A[12:1] of the CPU (considering a little endian CPU address bus)

3. At de-assertion READYB is driven to the inactive value (high) for a configurable time.

Table 1. Pin Descriptions

Pin Name

Pin Number

Dir

Description