XSMT

0.9 * DV

DD

t

r

t

f

<20ns

<20ns

0.1 * DV

DD

System Clock

(SCK)

"L"

"H"

0.3*DVDD

0.7*DVDD

PCM5100A, PCM5101A, PCM5102A

PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1

www.ti.com

SLAS859C – MAY 2012 – REVISED MAY 2015

8.6 Timing Requirements

Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low

phase jitter and noise.

MIN

TYP

MAX

UNIT

System clock pulse cycle time

20

1000

ns

DVDD = 1.8 V

8

System clock pulse width, High

ns

DVDD = 3.3 V

9

DVDD = 1.8 V

8

System clock pulse width, Low

ns

DVDD = 3.3 V

9

Figure 1. Timing Requirements for SCK Input

8.7 Timing Requirements, XSMT

MIN

TYP

MAX

UNIT

Rise time

20

ns

Fall time

20

ns

Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute

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