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TAS5414C-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TAS5414C-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 53 page  TAS5414C-Q1, TAS5424C-Q1 www.ti.com SLOS795E – SEPTEMBER 2013 – REVISED JANUARY 2015 Electrical Characteristics (continued) Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ, AES17 filter, default I 2C settings, master-mode operation (see Figure 21) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN, SHORT DIAGNOSTICS Maximum resistance to detect a short from RS2P, RS2G 200 Ω OUT pin(s) to PVDD or ground Minimum load resistance to detect open ROPEN_LOAD Including speaker wires 300 740 1300 Ω circuit Maximum load resistance to detect short RSHORTED_LOAD Including speaker wires 0.5 1 1.5 Ω circuit I2C ADDRESS DECODER tLATCH_I2CADDR 300 μs Time delay to latch I2C address after POR Voltage on I2C_ADDR pin for address 0 Connect to GND 0% 0% 15% Voltage on I2C_ADDR pin for address 1 25% 35% 45% External resistors in series between D_BYP and GND as VI2C_ADDR VD_BYP a voltage divider Voltage on I2C_ADDR pin for address 2 55% 65% 75% Voltage on I2C_ADDR pin for address 3 Connect to D_BYP 85% 100% 100% I2C Power-on hold time before I2C tHOLD_I2C STANDBY high 1 ms communication fSCL SCL clock frequency 400 kHz VIH SCL pin input voltage for logic-level high 2.1 5.5 V RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V VIL SCL pin input voltage for logic-level low –0.5 1.1 V I2C read, RI2C = 5-kΩ pullup, VOH SDA pin output voltage for logic-level high 2.4 V supply voltage = 3.3 V or 5 V VO SDA pin output voltage for logic-level low 0.4 V I2C read, 3-mA sink current I2C write, RI2C = 5-kΩ pullup, VIH SDA pin input voltage for logic-level high 2.1 5.5 V supply voltage = 3.3 V or 5 V I2C write, RI2C = 5-kΩ pullup, VIL SDA pin input voltage for logic-level low –0.5 1.1 V supply voltage = 3.3 V or 5 V C I Capacitance for SCL and SDA pins 10 pF OSCILLATOR OSC_SYNC pin output voltage for logic- VOH 2.4 V level high I2C_ADDR pin set to MASTER mode OSC_SYNC pin output voltage for logic- VOL 0.5 V level low OSC_SYNC pin input voltage for logic-level VIH 2 V high I2C_ADDR pin set to SLAVE mode OSC_SYNC pin input voltage for logic-level VIL 0.8 V low I2C_ADDR pin set to MASTER mode, fS = 500 kHz 3.76 4 4.24 fOSC_SYNC OSC_SYNC pin clock frequency I2C_ADDR pin set to MASTER mode, fS = 417 kHz 3.13 3.33 3.63 MHz I2C_ADDR pin set to MASTER mode, fS = 357 kHz 2.68 2.85 3.0 Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TAS5414C-Q1 TAS5424C-Q1 |
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