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TAS5421-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5421-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 33 page SCL SDA t h(2) t (buf) t su(2) t su(3) Start Condition Stop Condition T0028-02 SCL SDA t w(H) t w(L) t r t f t su(1) t h(1) T0027-03 TAS5421-Q1 www.ti.com SLOS814C – MARCH 2014 – REVISED JANUARY 2015 6.6 Timing Requirements for I 2C Interface Signals over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT f(SCL) SCL clock frequency 400 kHz tr Rise time for both SDA and SCL signals 300 ns tf Fall time for both SDA and SCL signals 300 ns tw(H) SCL pulse duration, high 0.6 μs tw(L) SCL pulse duration, low 1.3 μs tsu(2) Setup time for START condition 0.6 μs th(2) START condition hold time before generation of first clock pulse 0.6 μs tsu(1) Data setup time 100 ns th(1) Data hold time 0(1) ns tsu(3) Setup time for STOP condition 0.6 μs C(B) Load capacitance for each bus line 400 pF (1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. Figure 1. SCL and SDA Timing Figure 2. Timing for Start and Stop Conditions Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TAS5421-Q1 |
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