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TAS5630B Datasheet(PDF) 7 Page - Texas Instruments |
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TAS5630B Datasheet(HTML) 7 Page - Texas Instruments |
7 / 38 page TAS5630B www.ti.com SLES217D – NOVEMBER 2010 – REVISED MARCH 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range unless otherwise noted (1) MIN MAX UNIT VDD to AGND –0.3 13.2 V GVDD to AGND –0.3 13.2 V PVDD_X to GND_X(2) –0.3 69 V OUT_X to GND_X(2) –0.3 69 V BST_X to GND_X(2) –0.3 82.2 V BST_X to GVDD_X(2) –0.3 69 V VREG to AGND –0.3 4.2 V GND_X to GND –0.3 0.3 V GND_X to AGND –0.3 0.3 V OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO–, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF to AGND –0.3 4.2 V INPUT_X –0.3 7 V RESET, SD, OTW1, OTW2, CLIP, READY to AGND –0.3 7 V Continuous sink current (SD, OTW1, OTW2, CLIP, READY) 9 mA Operating junction temperature, TJ 0 150 °C Storage temperature, Tstg –40 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) These voltages represents the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. 6.2 ESD Ratings VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge V Charged-device model (CDM), per JEDEC specification JESD22- ±500 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD_x Half-bridge supply DC supply voltage 25 50 52.5 V GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V RL(BTL) 3.5 4 Output filter according to schematics in the RL(SE) (2) Load impedance (1) 1.8 2 Ω application information section RL(PBTL) (2) 2.4 3 LOUTPUT(BTL) 7 10 LOUTPUT(SE) (2) Output filter inductance (1) Minimum output inductance at IOC 7 15 μH LOUTPUT(PBTL) (2) 7 10 Nominal 385 400 415 PWM frame rate selectable for AM interference fPWM AM1 315 333 350 kHz avoidance; 1% resistor tolerance. AM2 260 300 335 Nominal; master mode 9.9 10 10.1 RFREQ_ADJ PWM frame-rate-programming resistor AM1; master mode 19.8 20 20.2 k Ω AM2; master mode 29.7 30 30.3 (1) Values are for actual measured impedance over all combinations of tolerance, current and temperature and not simply the component rating. (2) See additional details for SE and PBTL in System Design Considerations. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TAS5630B |
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