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TAS5768MRMTR Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5768MRMTR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 84 page  TAS5766M, TAS5768M www.ti.com SLAS965C – SEPTEMBER 2013 – REVISED JANUARY 2015 Pin Functions HTTSOP VQFN SYMBOL TYPE(1) DESCRIPTION PIN No. PIN No. ADR1 26 45 I LSB address select bit for I2C ADR2 20 39 I 2nd LSB address select bit for I2C AVCC 41 12 PI Analog Supply – connect to PVCC AVDD 14 33 PI Analog Supply BCLK 23 42 I Audio data bit clock input Boot strap negative Left channel output, connect to 220 nF X7R ceramic cap to BSNL 48 19 BST OUTNL Boot strap negative Right channel output, connect to 220 nF X7R ceramic cap to BSNR 1 20 BST OUTNR Boot strap positive Left channel output, connect to 220 nF X7R ceramic cap to BSPL 44 17 BST OUTPL Boot strap positive Right channel output, connect to 220 nF X7R ceramic cap to BSPR 5 22 BST OUTPR CAPM 34 5 Charge pump flying capacitor pin for negative rail CAPP 32 3 Charge pump flying capacitor pin for positive rail CPVDD 31 2 PI Charge pump power supply, 3.3 V DACL 36 7 O Analog output from DAC left channel, ground centered DACR 13 32 O Analog output from DAC Right channel, ground centered DIN 24 43 I Audio data input DVDD 30 1 PI Digital power supply, 3. 3 V FAULT 40 11 OD General fault reporting, Open Drain, High = normal operation, Low = fault condition GAIN/FSW 9 28 I Sets power stage Gain and selects output switching frequency 3, 10, 15, 4, 10, 14, 15, GND 29, 33, 39, 24, 25, 29, 34, G Ground 46 48 GPIO1 18 37 I/O General purpose digital input and output port GPIO2 19 38 I/O General purpose digital input and output port GPIO3 21 40 I/O General purpose digital input and output port GVDD 8 27 PBY Internal Gate drive supply, connect 1uF to GND INNL 38 9 I Negative audio input for Left channel. Internally biased at 3 V INNR 11 30 I Negative audio input for Right channel. Internally biased at 3 V INPL 37 8 I Positive audio input for Left channel. Internally biased at 3 V INPR 12 31 I Positive audio input for Right channel. Internally biased at 3 V LDOO 28 47 PBY Internal logic supply rail pin for decoupling, 1.8 V, connect 1 µF to GND LRCLK 25 44 I Audio data word clock input OUTNL 47 18 PO Negative Left channel output OUTNR 2 21 PO Negative Right channel output OUTPL 45 16 PO Positive Left channel output OUTPR 4 23 PO Positive Right channel output 6, 7, 42, PVCC 13, 26 PI 4.5-V to 26.4-V Power supply 43 SCL 17 36 I Input clock for I2C SCLK 22 41 I System clock input (also referred to as master clock input) SDA 16 35 I/O Input data for I2C Thermal 49 49 G Connect Thermal Pad to Ground pad VNEG 35 6 PO Negative charge pump rail pin for decoupling –3.3 V XSMT/UVP 27 46 I Soft mute control : Soft mute (Low) / soft un-mute (High) (1) TYPE: BST=Boot Strap, PO=Power Output, G = General Ground, I= Input, O= Output, I/O = Input or Output, , PBY=Power Bypass, , PI=Power Input,. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TAS5766M TAS5768M |
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