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C8051F855-C-GM Datasheet(PDF) 6 Page - Silicon Laboratories |
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C8051F855-C-GM Datasheet(HTML) 6 Page - Silicon Laboratories |
6 / 328 page 5 Rev. 1.0 20.4.1.Edge Aligned PWM152 20.4.2.Center Aligned PWM154 20.4.3. 8 to11-bit Pulse Width Modulator Modes156 20.4.4. 16-Bit Pulse Width Modulator Mode157 20.5.Comparator Clear Function158 20.6.PCA Control Registers159 21. Port I/O (Port 0, Port 1, Port 2, Crossbar, and Port Match)176 21.1.General Port I/O Initialization177 21.2.Assigning Port I/O Pins to Analog and Digital Functions178 21.2.1.Assigning Port I/O Pins to Analog Functions178 21.2.2.Assigning Port I/O Pins to Digital Functions178 21.2.3.Assigning Port I/O Pins to Fixed Digital Functions179 21.3.Priority Crossbar Decoder180 21.4.Port I/O Modes of Operation182 21.4.1.Configuring Port Pins For Analog Modes182 21.4.2.Configuring Port Pins For Digital Modes182 21.4.3.Port Drive Strength182 21.5.Port Match183 21.6.Direct Read/Write Access to Port I/O Pins183 21.7.Port I/O and Pin Configuration Control Registers184 22. Reset Sources and Supply Monitor202 22.1.Power-On Reset203 22.2.Power-Fail Reset / Supply Monitor204 22.3.Enabling the VDD Monitor204 22.4.External Reset205 22.5.Missing Clock Detector Reset205 22.6.Comparator0 Reset205 22.7.Watchdog Timer Reset205 22.8.Flash Error Reset205 22.9.Software Reset205 22.10.Reset Sources Control Registers206 22.11.Supply Monitor Control Registers207 23. Serial Peripheral Interface (SPI0)208 23.1.Signal Descriptions209 23.1.1.Master Out, Slave In (MOSI)209 23.1.2.Master In, Slave Out (MISO)209 23.1.3.Serial Clock (SCK)209 23.1.4.Slave Select (NSS)209 23.2.SPI0 Master Mode Operation210 23.3.SPI0 Slave Mode Operation212 23.4.SPI0 Interrupt Sources212 23.5.Serial Clock Phase and Polarity212 23.6.SPI Special Function Registers214 23.7.SPI Control Registers218 24. System Management Bus / I2C (SMBus0)222 |
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