+

+

±

±

+

+

±

±

+

±

+

±

PLIMIT

PLIMIT

Reference

Gain Control

TTL

Buffer

LDO

Regulator

Ramp

Generator

Biases and

References

Startup

Protection

Logic

SC Detect

DC Detect

Thermal

Detect

UVLO and

OVLO

Gate

Drive

Gate

Drive

PWM

Logic

AGND

GVDD

GVDD

AVCC

AVCC

PLIMIT

GAIN1

GAIN0

SD

FAULT

INN

INP

OUTN FB

Gain

Control

OUTP FB

GVDD

PVCC

PVCC

PVCC

PVCC

GVDD

OUTN FB

OUTP FB

OUTN

PGND

BSN

PGND

OUTP

BSP

TPA3111D1-Q1

www.ti.com

SLOS759E – MARCH 2012 – REVISED DECEMBER 2015

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 DC Detect

The TPA3111D1-Q1 circuitry protects the speakers from DC current which might occur because of defective

capacitors on the input or shorts on the printed circuit board at the inputs. A DC-detect fault is reported on the

FAULT pin as a low state. The DC-detect fault also causes the amplifier to shut down by changing the state of

the outputs to Hi-Z. To clear the DC detect, cycle the PVCC supply. Cycling SD does NOT clear a DC-detect

fault.

A DC-detect fault is issued when the output differential duty-cycle exceeds 14% (for example, 57%, –43%) for

more than 420 ms at the same polarity. This feature helps protect the speaker from large DC currents or AC

currents less than 2 Hz. To avoid nuisance faults because of the DC detect circuit, hold the SD pin low at power-

up until the signals at the inputs are stable. Also, match the impedance at the positive and negative input to

avoid nuisance DC-detect faults.

Table 1 lists the minimum differential input voltages required to trigger the DC detect. The inputs must remain at

or above the voltage listed in the table for more than 420 ms to trigger the DC detect.

Table 1. DC Detect Threshold

AV (dB)

20

112

26

56

32

28

36

17

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