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EFM32HG310 Datasheet(PDF) 6 Page - Silicon Laboratories |
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EFM32HG310 Datasheet(HTML) 6 Page - Silicon Laboratories |
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6 / 69 page  Preliminary ...the world's most energy friendly microcontrollers 2015-05-06 - EFM32HG310FXX - _Rev0.91 6 www.silabs.com 2.1.20 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per second. The integrated input mux can select inputs from 3 external pins and 6 internal signals. 2.1.21 Current Digital to Analog Converter (IDAC) The current digital to analog converter can source or sink a configurable constant current, which can be output on, or sinked from pin or ADC. The current is configurable with several ranges of various step sizes. 2.1.22 Advanced Encryption Standard Accelerator (AES) The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slave which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit operations are not supported. 2.1.23 General Purpose Input/Output (GPIO) In the EFM32HG310, there are 22 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 13 asynchronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other peripherals. 2.2 Configuration Summary The features of the EFM32HG310 is a subset of the feature set described in the EFM32HG Reference Manual. Table 2.1 (p. 6) describes device specific implementation of the features. Table 2.1. Configuration Summary Module Configuration Pin Connections Cortex-M0+ Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA USB Full configuration USB_VREGI, USB_VREGO, USB_DM, USB_DMPU, USB_DP I2C0 Full configuration I2C0_SDA, I2C0_SCL USART0 Full configuration with IrDA and I2S US0_TX, US0_RX. US0_CLK, US0_CS USART1 Full configuration with I2S and IrDA US1_TX, US1_RX, US1_CLK, US1_CS |
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