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EFM32HG322F64G-A-QFP48 Datasheet(PDF) 4 Page - Silicon Laboratories |
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EFM32HG322F64G-A-QFP48 Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 70 page Preliminary ...the world's most energy friendly microcontrollers 2015-05-06 - EFM32HG322FXX - _Rev0.91 4 www.silabs.com There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. 2.1.4 Direct Memory Access Controller (DMA) The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA controller licensed from ARM. 2.1.5 Reset Management Unit (RMU) The RMU is responsible for handling the reset functionality of the EFM32HG. 2.1.6 Energy Management Unit (EMU) The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32HG microcon- trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks. 2.1.7 Clock Management Unit (CMU) The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32HG. The CMU provides the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not wasting power on peripherals and oscillators that are inactive. 2.1.8 Watchdog (WDOG) The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli- cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a software failure. 2.1.9 Peripheral Reflex System (PRS) The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but edge triggers and other functionality can be applied by the PRS. 2.1.10 Low Energy USB The unique Low Energy USB peripheral provides a full-speed USB 2.0 compliant device controller and PHY with ultra-low current consumption. The device supports both full-speed (12MBit/s) and low speed (1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crys- tal-free operation. No external components are required. The Low Energy Mode ensures the current consumption is optimized and enables USB communication on a strict power budget. The USB device includes an internal dedicated descriptor-based Scatter/Gather DMA and supports up to 3 OUT end- points and 3 IN endpoints, in addition to endpoint 0. The on-chip PHY includes software controllable pull-up and pull-down resistors. 2.1.11 Inter-Integrated Circuit Interface (I2C) The I 2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast- mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s. |
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