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EFM32LG232F64G-E-QFP64 Datasheet(PDF) 7 Page - Silicon Laboratories

Part # EFM32LG232F64G-E-QFP64
Description  Output state retention and wake-up from Shutoff Mode
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EFM32LG232F64G-E-QFP64 Datasheet(HTML) 7 Page - Silicon Laboratories

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...the world's most energy friendly microcontrollers
2014-06-13 - EFM32LG232FXX - d0106_Rev1.30
7
www.silabs.com
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.27 General Purpose Input/Output (GPIO)
In the EFM32LG232, there are 53 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32LG232 is a subset of the feature set described in the EFM32LG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]


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