LMK03318RHST datasheet(10/136 Pages) TI1

Part #	LMK03318RHST

Description	Ultra-Low-Noise Jitter Clock Generator Family

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Manufacturer	TI1 [Texas Instruments]

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LMK03318

SNAS669A – SEPTEMBER 2015 – REVISED DECEMBER 2015

www.ti.com

8.11 PLL Characteristics

VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to

+85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fPD

Phase detector frequency

1

150

MHz

PN1Hz

PLL figure of merit(1)

–231

dBc/Hz

PN10kHz

PLL 1/f noise at 10 kHz offset ICP = 6.4 mA, 25 MHz phase detector

–136

dBc/Hz

normalized to 1 GHz(2)

ICP-HIZ

Charge-pump leakage in Hi-Z

55

nA

Mode

(1)

PLL flat phase noise = PN1 Hz + 20 × log(N) + 10 × log(fPD), with wide loop bandwidth and away from1/f noise region.

(2)

Phase noise normalized to 1 GHz. PLL 1/f phase noise = PN10 kHz + 20 × log(FOUT/1 GHz) – 10 × log(offset/10 kHz)

8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])

VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDDO_x = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to

+85°C, outputs loaded with 2 pF to GND

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT

Output frequency

1

200

MHz

VOH

(2)

Output high voltage

IOH = 1 mA

1.35

V

VOL

Output low voltage

IOL = 1 mA

0.35

V

IOH

Output high current

21

mA

IOL

Output low current

–21

mA

tR/tF

Output rise/fall time

20% to 80%

250

ps

tSKEW

(3)

Output-to-output skew

same divide value

100

ps

tSKEW

(3)

Output-to-output skew

LVCMOS-to-differential; same divide value

1.5

ns

tPROP-CMOS IN-to-OUT propagation delay

PLL Bypass

1

ns

PN-Floor

Output phase noise floor

66.66 MHz

–155

dBc/Hz

(fOFFSET > 10 MHz)

ODC(3)

Output Duty Cycle

45%

55%

ROUT

Output Impedance

50

Ω

(1)

Refer to Parameter Measurement Information for relevant test conditions.

(2)

VOH level is NOT rail-to-rail for VDDO = 2.5 V or 3.3 V, 1.8-V LVCMOS output buffer supply is internally regulated down to 1.8 V.

(3)

Ensured by characterization.

8.13 LVCMOS Output Characteristics (STATUS[1:0]

VDD_IN, VDD_PLL, VDD_LDO, VDD_DIG = 3.3 V ± 5%, VDD_O = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA = –40°C to 85°C,

outputs loaded with 2 pF to GND

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT

Output frequency

3.75

200

MHz

VOH

Output high voltage

IOH = 1 mA

2.5

V

VOL

Output low voltage

IOL = 1 mA

0.6

V

IOH

Output high current

33

mA

IOL

Output low current

-33

mA

tR/tF

(2)

Output rise/fall time

20% to 80%, R49[3-2], R49[1:0] = 10

2.1

ns

20% to 80%, R49[3-2], R49[1-0] = 00

0.35

ns

PN-Floor

Output phase noise floor

66.66 MHz

-148

dBc/Hz

(fOFFSET > 10 MHz)

ODC(2)

Output duty cycle

45%

55%

ROUT

Output impedance

50

Ω

(1)

Refer to Parameter Measurement Information for relevant test conditions.

(2)

Ensured by characterization.

10

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