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SI52143 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI52143 Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 21 page Si52143 Rev 1.3 5 Table 2. AC Electrical Specification Parameter Symbol Test Condition Min Typ Max Unit Crystal Long-term Accuracy LACC Measured at VDD/2 differential — — 250 ppm Clock Input Duty Cycle TDC Measured at VDD/2 45 — 55 % CLKIN Rising and Falling Slew Rate TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 µA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — µA DIFF at 0.7 V Duty Cycle TDC Measured at 0 V differential 45 — 55 % Output-to-Output Skew TSKEW Measured at 0 V differential — — 50 ps Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter, Common Clock Pk-Pk PCIe Gen 1 040 50ps PCIe Gen 2 Phase Jitter, Common Clock RMSGEN2 10 kHz < F < 1.5 MHz 0 2 2.6 ps 1.5 MHz< F < Nyquist Rate 0 2 2.6 ps PCIe Gen 3 Phase Jitter, Common Clock RMSGEN3 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz 00.5 0.9ps PCIe Gen 3 Phase Jitter, Separate Reference No Spread, SRNS RMSGEN3_SRNS PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — 0.35 0.64 ps PCIe Gen 4 Phase Jitter, Common Clock RMSGEN4 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz —0.5 0.9 ps Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm Rising/Falling Slew Rate TR / TF Measured differentially from ±150 mV 1— 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V Crossing Point Voltage at 0.7 V Swing VOX 300 — 550 mV Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
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