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SI53019-A01A Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI53019-A01A Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 37 page Rev. 1.3 1/16 Copyright © 2016 by Silicon Laboratories Si53019-A01A Si53019-A01A 19-O UTPUT PCI E G EN 3 B UFFER Features Applications Description The Si53019-A01A is a 19-output, current mode HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Nineteen 0.7 V current-mode, HCSL PCIe Gen 3 outputs 100 MHz /133 MHz PLL operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch value from HW pin 9 selectable SMBus addresses Fixed external feedback path 8 dedicated OE pin PLL or bypass mode Spread spectrum tolerable 50 ps output-to-output skew Fixed 0 ps input to output delay Low phase jitter (Intel QPI, PCIe Gen 1/Gen 2/Gen 3/Gen 4 common clock compliant Gen 3 SRNS Compliant 100 ps input-to-output delay Extended Temperature: –40 to 85 °C Package: 72-pin QFN Server Storage Data Center Network Security Patents pending Ordering Information: See page 32. Pin Assignments Si53019-A01A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 VDDA GNDA HBW_BYPASS_LBW PWRGD / PWRDN GND VDDR CLK_IN CLK_IN SA_0 SDA SCL SA_1 FB_OUT GND DIF_7 DIF_7 OE6 VDD 48 47 46 45 44 43 42 41 40 39 38 37 DIF_11 DIF_11 DIF_10 DIF_10 DIF_9 DIF_9 DIF_8 DIF_8 54 53 52 51 50 49 18 17 OE7 OE10 FB_OUT IREF FB_IN FB_IN 100M_133M OE8 OE11 OE9 |
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