SI53302 datasheet(1/34 Pages) SILABS

Part #	SI53302

Description	1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX

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Manufacturer	SILABS [Silicon Laboratories]

Direct Link	http://www.silabs.com

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Rev. 1.1 9/14

Si53302

1:10 L OW J ITTER U NIVERSAL B UFFER/L EVEL

TRANSLATOR WITH 2:1 I NPUT M UX

Features

Applications

Description

The Si53302 is an ultra low jitter ten output differential buffer with pin-selectable

output clock signal format and divider selection. The Si53302 features a 2:1 mux

with glitchless switching, making it ideal for redundant clocking applications. The

Si53302 utilizes Silicon Laboratories' advanced CMOS technology to fanout

clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low

propagation delay variability. The Si53302 features minimal cross-talk and

provides superior supply noise rejection, simplifying low jitter clock distribution in

noisy environments. Independent core and output bank supply pins provide

integrated level translation without the need for external circuitry.

Functional Block Diagram



10 differential or 20 LVCMOS outputs



Ultra-low additive jitter: 45 fs rms



Wide frequency range: 1 to 725 MHz



Any-format input with pin selectable

output formats: LVPECL, Low Power

LVPECL, LVDS, CML, HCSL,

LVCMOS



2:1 clock input mux



Glitchless input clock switching



Synchronous output enable



Output clock division: /1, /2, /4



Independent VDD and VDDO:

1.8/2.5/3.3 V



1.2/1.5 V LVCMOS output support



Excellent power supply noise

rejection (PSRR)



Selectable LVCMOS drive strength to

tailor jitter and EMI performance



Loss of signal (LOS) monitors for

loss of input clock



Small size: 44-QFN (7 mm x 7 mm)



RoHS compliant, Pb-free



Industrial temperature range:

–40 to +85 °C



High-speed clock distribution



Ethernet switch/router



Optical Transport Network (OTN)



SONET/SDH



PCI Express Gen 1/2/3



Storage



Telecom



Industrial



Servers



Backplane clock distribution

Vref

DivA

DivB

VDD

Power

Supply

Filtering

Vref

Generator

/Q0, /Q1, /Q2, /Q3, /Q4

CLK0

LOS

Monitor

LOS0

/Q5, /Q6, /Q7, /Q8, /Q9

Q5, Q6, Q7, Q8, Q9

CLK1

CLK_SEL

Switching

Logic

LOS1

VDDOA

SFOUTA[1:0]

OEA

DIVA

Q0, Q1, Q2, Q3, Q4

DIVB

VDDOB

SFOUTB[1:0]

OEB

Bank A

Bank B

Patents pending

Ordering Information:

See page 29.

Pin Assignments

GND

PAD

27

26

25

24

23

29

28

30

32

31

33

7

8

9

10

11

5

6

4

2

3

1

CLK_SEL

Q0

Q1

Q2

Q7

Q8

Q9

GND

DIVA

SFOUTA[1]

SFOUTA[0]

DIVB

SFOUTB[1]

SFOUTB[0]

NC

Si53302

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