Si53301

Rev. 1.1

7

Minimum Input Clock

Slew Rate1

SR

Required to meet prop delay and

additive jitter specifications

(20–80%)

0.75

—

—

V/ns

Output Rise/Fall Time

LVDS, 20/80%

—

—

325

ps

LVPECL, 20/80%

—

—

350

ps

HCSL2, 20/80%

—

—

280

ps

CML, 20/80%

—

—

350

ps

Low-Power LVPECL, 20/80%

—

—

325

ps

LVCMOS 200 MHz, 20/80%,

2pF load

——

750

ps

Minimum Input Pulse

Width

500

—

—

ps

Propagation Delay

LVCMOS (12mA drive with no load)

1250

2000

2750

ps

LVPECL, LVDS

600

800

1000

ps

Output Enable Time

F=1MHz

—

2500

—

ns

F = 100 MHz

—

30

—

ns

F = 725 MHz

—

5

—

ns

Output Disable Time

F=1MHz

—

2000

—

ns

F = 100 MHz

—

30

—

ns

F = 725 MHz

—

5

—

ns

Output to Output Skew3

LVCMOS (12 mA drive to no load)

—

50

120

ps

LVPECL

—

35

70

ps

LVDS

—

35

70

ps

Part to Part Skew4

Differential

—

—

150

ps

Table 10. AC Characteristics (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1.

When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required.

2.

HCSL measurements were made with receiver termination. See Figure 9 on page 19.

3.

Output to Output skew specified for outputs with an identical configuration.

4.

Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and

equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross

points.

5.

amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details.