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LMK61PD0A2 Datasheet(PDF) 1 Page - Texas Instruments |
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LMK61PD0A2 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 27 page OS OUTN VDD OE GND OUTP FS0 FS1 1 6 2 5 4 3 7 8 LMK61PD0A2 Ultra-high performance oscillator PLL Output Divider Output Buffer Power Conditioning Interface ROM (Pin Control) Integrated Oscillator Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator 1 Features 3 Description The LMK61PD0A2 is an ultra-low jitter PLLatinumTM 1 • Ultra-low Noise, High Performance pin selectable oscillator that generates commonly – Jitter: 90 fs RMS typical fOUT > 100 MHz used reference clocks. The device is pre- – PSRR: -70 dBc, robust supply noise immunity programmed in factory to support seven unique reference clock frequencies that can be selected by • Flexible Output Frequency and Format; User pin-strapping each of FS[1:0] to VDD, GND or NC (no Selectable connect). Output format is selected between – Frequencies: 62.5 MHz, 100 MHz, 106.25 LVPECL, LVDS, or HCSL by pin-strapping OS to MHz, 125 MHz, 156.25 MHz, 212.5 MHz, VDD, GND or NC. Internal power conditioning provide 312.5 MHz excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power – Formats: LVPECL, LVDS or HCSL delivery network. The device operates from a single • Total frequency tolerance of ± 50 ppm 3.3 V ± 5% supply. • Internal memory stores multiple start-up configurations, selectable through pin control Device Information(1) • 3.3V operating voltage PART NUMBER PACKAGE BODY SIZE (NOM) • Industrial temperature range (-40ºC to +85ºC) LMK61PD0A2 8-pin QFM (SIA) 7.0 mm x 5.0 mm • 7 mm x 5 mm 8-pin package (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • High-performance replacement for crystal-, SAW-, or silicon-based Oscillators • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN • Test and Measurement • Medical Imaging • FPGA, Processor Attach Pinout and Simplified Block Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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