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LMK00338RTAT Datasheet(PDF) 7 Page - Texas Instruments |
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LMK00338RTAT Datasheet(HTML) 7 Page - Texas Instruments |
7 / 33 page LMK00338 www.ti.com SNAS636A – DECEMBER 2013 – REVISED OCTOBER 2014 Electrical Characteristics (continued) Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ TA ≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCLKin0 = 100 MHz -84 fCLKin0 = 200 MHz -82 fOFFSET > 50 kHz, ISOMUX Mux Isolation, CLKin0 to CLKin1 dBc PCLKinX = 0 dBm fCLKin0 = 500 MHz -71 fCLKin0 = 1000 MHz -65 CRYSTAL INTERFACE (OSCin, OSCout) FCLK External Clock Frequency Range(5) OSCin driven single-ended, OSCout floating 250 MHz Fundamental mode crystal ESR ≤ 200 Ω (10 FXTAL Crystal Frequency Range 10 40 MHz to 30 MHz) ESR ≤ 125 Ω (30 to 40 MHz)(8) CIN OSCin Input Capacitance 1 pF HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout Output Frequency Range(5) RL = 50 Ω to GND, CL ≤ 5 pF DC 400 MHz PCIe Gen 3, Additive RMS Phase Jitter for PCIe CLKin: 100 MHz, JitterADD_PCle PLL BW = 2–5 MHz, 0.03 0.15 ps 3.0(5) Slew rate ≥ 0.6 V/ns CDR = 10 MHz CLKin: 100 MHz, 77 Slew rate ≥ 3 V/ns Additive RMS Jitter Integration Vcco = 3.3 V, JitterADD fs Bandwidth to 20 MHz(9)(10) RT = 50 Ω to GND CLKin: 156.25 MHz, 86 Slew rate ≥ 2.7 V/ns CLKin: 100 MHz, -161.3 Slew rate ≥ 3 V/ns Vcco = 3.3 V, Noise Floor Noise Floor fOFFSET ≥ 10 MHz (9) (10) dBc/Hz RT = 50 Ω to GND CLKin: 156.25 MHz, -156.3 Slew rate ≥ 2.7 V/ns DUTY Duty Cycle(5) 50% input clock duty cycle 45% 55% 520 810 920 mV VOH Output High Voltage TA = 25 °C, DC Measurement, RT = 50 Ω to GND -150 0.5 150 mV VOL Output Low Voltage 160 350 460 mV VCROSS Absolute Crossing Voltage(5)(11) RL = 50 Ω to GND, CL ≤ 5 pF 140 mV ΔVCROSS Total Variation of VCROSS tR Output Rise Time 20% to 80%(11)(7) 250 MHz, Uniform transmission line up to 10 300 500 ps in. with 50- Ω characteristic impedance, tF Output Fall Time 80% to 20%(11)(7) 300 500 ps RL = 50 Ω to GND, CL ≤ 5 pF (8) The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations. (9) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. (10) Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs. (11) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMK00338 |
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