LMK04805 datasheet(5/139 Pages) TI1

Part #	LMK04805

Description	Low-Noise Clock Jitter Cleaner

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Manufacturer	TI1 [Texas Instruments]

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LMK04803, LMK04805, LMK04806, LMK04808

www.ti.com

SNAS489K – MARCH 2011 – REVISED DECEMBER 2014

Pin Functions(1) (continued)

I/O

TYPE

DESCRIPTION

NUMBER

NAME

19, 20

CLKout4, CLKout4*

O

Programmable

Clock output 4 (clock group 2).

21, 22

CLKout5*, CLKout5

O

Programmable

Clock output 5 (clock group 2).

23

GND

PWR

Ground.

24

Vcc4

PWR

Power supply for digital.

CLKin1, CLKin1*

Reference Clock Input Port 1 for PLL1. AC or DC Coupled.

Feedback input for external clock feedback input (0-delay

FBCLKin, FBCLKin*

25, 26

I

ANLG

mode). AC or DC Coupled.

External VCO input (External VCO mode). AC or DC

Fin/Fin*

Coupled.

Programmable status pin, default readback output.

27

Status_Holdover

I/O

Programmable

Programmable to holdover mode indicator. Other options

available by programming.

Reference Clock Input Port 0 for PLL1.

28, 29

CLKin0, CLKin0*

I

ANLG

AC or DC Coupled.

30

Vcc5

PWR

Power supply for clock inputs and OSCout1.

31, 32

OSCout1, OSCout1*

O

LVPECL

Buffered output 1 of OSCin port.

Programmable status pin, default lock detect for PLL1 and

33

Status_LD

I/O

Programmable

PLL2. Other options available by programming.

34

CPout1

O

ANLG

Charge pump 1 output.

35

Vcc6

PWR

Power supply for PLL1, charge pump 1.

Feedback to PLL1, Reference input to PLL2.

36, 37

OSCin, OSCin*

I

ANLG

AC Coupled.

38

Vcc7

PWR

Power supply for OSCin, OSCout0, and PLL2 circuitry.(2)

39, 40

OSCout0, OSCout0*

O

Programmable

Buffered output 0 of OSCin port.(2)

41

Vcc8

PWR

Power supply for PLL2, charge pump 2.

42

CPout2

O

ANLG

Charge pump 2 output.

43

Vcc9

PWR

Power supply for PLL2.

44

LEuWire

I

CMOS

MICROWIRE Latch Enable Input.

45

CLKuWire

I

CMOS

MICROWIRE Clock Input.

46

DATAuWire

I

CMOS

MICROWIRE Data Input.

47

Vcc10

PWR

Power supply for clock group 3: CLKout6 and CLKout7.

48, 49

CLKout6, CLKout6*

O

Programmable

Clock output 6 (clock group 3).

50, 51

CLKout7*, CLKout7

O

Programmable

Clock output 7 (clock group 3).

52

Vcc11

PWR

Power supply for clock group 4: CLKout8 and CLKout9.

53, 54

CLKout8, CLKout8*

O

Programmable

Clock output 8 (clock group 4).

55, 56

CLKout9*, CLKout9

O

Programmable

Clock output 9 (clock group 4).

57

Vcc12

PWR

Power supply for clock group 5: CLKout10 and CLKout11.

CLKout10,

58, 59

O

Programmable

Clock output 10 (clock group 5).

CLKout10*

CLKout11*,

60, 61

O

Programmable

Clock output 11 (clock group 5).

CLKout11

Programmable status pin. Default is input for pin control of

62

Status_CLKin0

I/O

Programmable

PLL1 reference clock selection. CLKin0 LOS status and

other options available by programming.

Programmable status pin. Default is input for pin control of

63

Status_CLKin1

I/O

Programmable

PLL1 reference clock selection. CLKin1 LOS status and

other options available by programming.

64

Vcc13

PWR

Power supply for clock group 0: CLKout0 and CLKout1.

DAP

–

GND

DIE ATTACH PAD, connect to GND.

(2)

See Vcc5 (CLKin and OSCout1), Vcc7 (OSCin and OSCout0) for information on configuring device for optimum performance.

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