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LMK04805 Datasheet(PDF) 7 Page - Texas Instruments |
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LMK04805 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 139 page  LMK04803, LMK04805, LMK04806, LMK04808 www.ti.com SNAS489K – MARCH 2011 – REVISED DECEMBER 2014 6.4 Thermal Information LMK0480x THERMAL METRIC(1) NKD UNIT 64 PINS RθJA Junction-to-ambient thermal resistance on 4-layer JEDEC PCB(2)(3) 25.2 RθJC(top) Junction-to-case (top) thermal resistance(4)(5) 6.9 RθJB Junction-to-board thermal resistance(6) 4.0 °C/W ψJT Junction-to-top characterization parameter(7) 0.1 ψJB Junction-to-board characterization parameter(8) 4.0 RθJC(bot) Junction-to-case (bottom) thermal resistance(9) 0.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) Specification assumes 32 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC PCB. These vias play a key role in improving the thermal performance of the WQFN. Note that the JEDEC PCB is a standard thermal measurement PCB and does not represent best performance a PCB can achieve. It is recommended that the maximum number of vias be used in the board layout. R θJA is unique for each PCB. (4) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (5) Case is defined as the DAP (die attach pad) (6) The junction-to-board thermal resistance is obtained by simulating an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). (9) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 6.5 Electrical Characteristics 3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C, at the Recommended Operating Conditions at the time of product characterization and are not specified. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION No DC path to ground on ICC_PD Power down supply current 1 3 mA OSCout1/1*(2) All clock delays disabled, CLKoutX_Y_DIV = 1045, ICC_CLKS Supply current with all clocks enabled(3) 505 590 mA CLKoutX_TYPE = 1 (LVDS), PLL1 and PLL2 locked. CLKin0/0* and CLKin1/1* INPUT CLOCK SPECIFICATIONS fCLKin Clock input frequency(4) 0.001 500 MHz SLEWCLKin (1) Clock input slew rate(5) 20% to 80% 0.15 0.5 V/ns VIDCLKin 0.25 1.55 |V| AC coupled Clock input CLKinX_BUF_TYPE = 0 (Bipolar) VSSCLKin 0.5 3.1 Vpp Differential input voltage (see (6) and VIDCLKin 0.25 1.55 |V| AC coupled Figure 4) CLKinX_BUF_TYPE = 1 (MOS) VSSCLKin 0.5 3.1 Vpp (1) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. (2) If emitter resistors are placed on the OSCout1/1* pins, there will be a DC current to ground which will cause powerdown Icc to increase. (3) Load conditions for output clocks: LVDS: 100- Ω differential. See Current Consumption and Power Dissipation Calculations for Icc for specific part configuration and how to calculate Icc for a specific design. (4) CLKin0, CLKin1 maximum is specified by characterization, production tested at 200 MHz. (5) Specified by characterization. (6) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages. Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808 |
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