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SI4827 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI4827 Datasheet(HTML) 5 Page - Silicon Laboratories |
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5 / 71 page  AN610 Rev. 0.3 5 The ATDD device is a slave device and its seven-bit device address is (0010001b). To achieve acceptable or higher tune frequency update performance, the system controller 2-wire bus mode clock speed of 10 kHz* or higher is recommended. The ATDD device requires a 32.768 kHz clock supply of 100 ppm for proper radio operation. The system controller can configure the ATDD device by applying an external reference clock to the device (various frequencies can be selected) or by using a 32.768 kHz crystal instead. The ATDD device has flexibility in selecting bands and configuring band properties, such as band top, band bottom, and channel spacing. In addition, the Si4822/26/40/44 SSOP24 packaged parts have a pull up resistor option (at pin 1 LNA_EN) to force the ATDD device to use its default band properties rather than the values programmed by the system controller. For example, when the ATDD device pin 1 is pulled up, it will ignore the band properties programmed by the system controller programmed (band top, band bottom, channel space, FM de-emphasis, and FM blend RSSI mono/stereo thresholds). The system controller is able to read this information from the band configuration state bits from the ATDD device. The Si4827 SOIC16 package ATDD part doesn't have the pin pull-up option. However, the host controller can send an extra argument byte in the ATDD_POWER_UP command to specify this band properties priority. *Note: The ATDD device requires a slower I2C clock for proper powerup immediately after a hardware reset; i.e., no higher than 10 kHz is recommended. After the powerup command sequence is succeeded, the host controller can switch to a higher speed. To power up the ATDD device for higher I2C clock speed, the host controller needs to obey more strict timing requirements as below: 1. After reset, the host controller needs to wait till the first IRQ pulse is finished before sending a command; i.e. send a command after the IRQ falling edge or wait 2.5 ms after the IRQ rising edge. 2. The pulse width of the I2C clock signal (i.e., high to low level ratio) must be equal or greater than 50%. 3. After sending either the ATDD_GET_STATUS command 0xE0 or the ATDD_POWER_UP command 0xE1, the host controller needs to wait for 2 ms before polling response byte CTS bit or reading the response directly. Following the above timing requirements, the ATDD device is tested by powering up successfully for I2C clock speed up to 50 kHz. Clock speed higher than 50 kHz is possible but is not guaranteed. After reset and the first successful powerup, the host controller is free to switch to a higher I2C speed and shorter CTS polling interval (down to 50 µs is recommended). Customers using 10 kHz I2C clock speed or below for powerup are not required to change their existing host controller firmware with respect to the new timing requirements. Table 2. ATDD Device Hardware Interface Pin Name Function RSTb Device reset input (active low) IRQ Host interrupt request output (active high) SDIO 2-wire bus mode serial data input/output SCLK 2-wire bus mode serial clock input (Note: ATDD device is slave) |
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