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DLP6500FYE Datasheet(PDF) 5 Page - Texas Instruments |
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DLP6500FYE Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 51 page  5 DLP6500FYE www.ti.com DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016 Product Folder Links: DLP6500FYE Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Table 1. Pin Functions (continued) PIN(1) TYPE (I/O/P) SIGNAL DATA RATE(2) INTERNAL TERM(3) DESCRIPTION TRACE (mils)(4) NAME NO. D_BN(8) T23 Input LVDS DDR Differential Data, Negative 484.45 D_BN(9) Z25 Input LVDS DDR Differential Data, Negative 492.09 D_BN(10) X24 Input LVDS DDR Differential Data, Negative 497.72 D_BN(11) W25 Input LVDS DDR Differential Data, Negative 495.16 D_BN(12) V25 Input LVDS DDR Differential Data, Negative 484.17 D_BN(13) T25 Input LVDS DDR Differential Data, Negative 481.42 D_BN(14) N25 Input LVDS DDR Differential Data, Negative 495.16 D_BN(15) U24 Input LVDS DDR Differential Data, Negative 489.8 D_BP(0) Y14 Input LVDS DDR Differential Data, Positive 494.88 D_BP(1) Z16 Input LVDS DDR Differential Data, Positive 486.26 D_BP(2) Y17 Input LVDS DDR Differential Data, Positive 495.16 D_BP(3) P23 Input LVDS DDR Differential Data, Positive 492.48 D_BP(4) Z19 Input LVDS DDR Differential Data, Positive 495.16 D_BP(5) N23 Input LVDS DDR Differential Data, Positive 497.99 D_BP(6) Y20 Input LVDS DDR Differential Data, Positive 495.16 D_BP(7) R24 Input LVDS DDR Differential Data, Positive 492.05 D_BP(8) R23 Input LVDS DDR Differential Data, Positive 484.45 D_BP(9) Y25 Input LVDS DDR Differential Data, Positive 492.24 D_BP(10) W24 Input LVDS DDR Differential Data, Positive 495.16 D_BP(11) X25 Input LVDS DDR Differential Data, Positive 494.72 D_BP(12) U25 Input LVDS DDR Differential Data, Positive 483.78 D_BP(13) R25 Input LVDS DDR Differential Data, Positive 489.13 D_BP(14) P25 Input LVDS DDR Differential Data, Positive 499.53 D_BP(15) V24 Input LVDS DDR Differential Data, Positive 488.66 SERIAL CONTROL SCTRL_AN C23 Input LVDS DDR Differential Serial Control, Negative 492.95 SCTRL_BN Y23 Input LVDS DDR Differential Serial Control, Negative 493.78 SCTRL_AP C24 Input LVDS DDR Differential Serial Control, Positive 493.78 SCTRL_BP Y24 Input LVDS DDR Differential Serial Control, Positive 493.11 CLOCKS DCLK_AN B23 Input LVDS Differential Clock, Negative 480.35 DCLK_BN Z23 Input LVDS Differential Clock, Negative 486.22 DCLK_AP B22 Input LVDS Differential Clock, Positive 485.83 DCLK_BP Z22 Input LVDS Differential Clock, Positive 491.93 SERIAL COMMUNICATIONS PORT (SCP) SCP_DO B8 Output LVCMOS SDR Serial Communications Port Output SCP_DI B7 Input LVCMOS SDR Pull-Down Serial Communications Port Data Input SCP_CLK B6 Input LVCMOS Pull-Down Serial Communications Port Clock SCP_ENZ C8 Input LVCMOS Pull-Down Active-low Serial Communications Port Enable MICROMIRROR RESET CONTROL RESET_ADDR(0) X9 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(1) X8 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(2) Z8 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(3) Z7 Input LVCMOS Pull-Down Reset Driver Address Select RESET_MODE(0) W11 Input LVCMOS Pull-Down Reset Driver Mode Select RESET_MODE(1) Z10 Input LVCMOS Pull-Down Reset Driver Mode Select RESET_SEL(0) Y10 Input LVCMOS Pull-Down Reset Driver Level Select RESET_SEL(1) Y9 Input LVCMOS Pull-Down Reset Driver Level Select |
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