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DLP9000XFLS Datasheet(PDF) 10 Page - Texas Instruments |
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DLP9000XFLS Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 56 page  DLP9000 DLPS036A – SEPTEMBER 2014 – REVISED OCTOBER 2015 www.ti.com Pin Functions (continued) PIN TYPE SIGNAL DESCRIPTION (I/O/P) NAME (1) NO. NO. NO. VSS AJ25 AK6 AK12 Power Analog Device Ground. Common return for all power. VSS AK18 AL29 Power Analog Device Ground. Common return for all power. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT SUPPLY VOLTAGES VCC Supply voltage for LVCMOS core logic (2) –0.5 4 V VCCI Supply voltage for LVDS receivers (2) –0.5 4 V VOFFSET Supply voltage for HVCMOS and micromirror electrode (2) (3) –0.5 9 V VBIAS Supply voltage for micromirror electrode (2) –0.5 17 V VRESET Supply voltage for micromirror electrode (2) –11 0.5 V | VCC – VCCI | Supply voltage delta (absolute value) (4) 0.3 V | VBIAS – VOFFSET | Supply voltage delta (absolute value) (5) 8.75 V INPUT VOLTAGES Input voltage for all other LVCMOS input pins (2) –0.5 VCC + 0.3 V Input voltage for all other LVDS input pins (2) (6) –0.5 VCCI + 0.3 V | VID | Input differential voltage (absolute value) (7) 700 mV IID Input differential current (7) 7 mA CLOCKS DLP9000FLS Clock frequency for LVDS interface, DCLK_A 460 MHz Clock frequency for LVDS interface, DCLK_B 460 MHz Clock frequency for LVDS interface, DCLK_C 460 MHz Clock frequency for LVDS interface, DCLK_D 460 MHz ƒclock DLP9000XFLS Clock frequency for LVDS interface, DCLK_A 500 MHz Clock frequency for LVDS interface, DCLK_B 500 MHz Clock frequency for LVDS interface, DCLK_C 500 MHz Clock frequency for LVDS interface, DCLK_D 500 MHz ENVIRONMENTAL Case temperature: operational (8) (9) 0 70 ºC TCASE Case temperature: non–operational (9) –40 80 ºC TGRADIENT Differential temperature (8) 10 ºC Operating relative humidity (non-condensing) 0 95% RH (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability. (2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected (3) VOFFSET supply transients must fall within specified voltages. (4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. (5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Recommendations for additional information. (6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential. (7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. (8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential temperature, or illumination power density may affect device reliability. (9) DMD Temperature is the worst-case of any test point shown in Figure 15, or the active array as calculated by the Micromirror Array Temperature Calculation. 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DLP9000 |
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