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DLP9500UVFLN Datasheet(PDF) 3 Page - Texas Instruments |
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DLP9500UVFLN Datasheet(HTML) 3 Page - Texas Instruments |
3 / 54 page DLP9500UV www.ti.com DLPS033B – NOVEMBER 2014 – REVISED JUNE 2015 5 Description (continued) Electrically, the DLP9500UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by- row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller. 6 Pin Configuration and Functions FLN Package 355-Pin LCCC Bottom View Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DLP9500UV |
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