DLP9500UVFLN datasheet(3/54 Pages) TI1

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DLP9500UVFLN Datasheet(PDF) 3 Page - Texas Instruments

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DLP9500UV

www.ti.com

DLPS033B – NOVEMBER 2014 – REVISED JUNE 2015

5 Description (continued)

Electrically, the DLP9500UV consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid

of 1920 memory cell columns by 1080 memory cell rows. The CMOS memory array is addressed on a row-by-

row basis, over four 16-bit LVDS DDR buses. Addressing is handled by a serial control bus. The specific CMOS

memory access protocol is handled by the DLPC410 digital controller.

6 Pin Configuration and Functions

FLN Package

355-Pin LCCC

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Product Folder Links: DLP9500UV

Manufacturer	Part #	Datasheet	Description
Texas Instruments	DLP9500	1Mb / 54P	[Old version datasheet] LVDS Type A DMD
	DLP9500BFLN	1Mb / 54P	[Old version datasheet] LVDS Type A DMD
	DLP9500FLN	1Mb / 54P	[Old version datasheet] LVDS Type A DMD

Manufacturer	Part #	Datasheet	Description
Texas Instruments	DLP7000UV	1Mb / 51P	[Old version datasheet] LVDS Type A DMD
	DLP9500	1Mb / 54P	[Old version datasheet] LVDS Type A DMD
	DLP7000	1Mb / 52P	[Old version datasheet] LVDS Type A DMD
	DLP6500FLQ	601Kb / 49P	[Old version datasheet] MVSP Type A DMD
	DLP6500	669Kb / 50P	[Old version datasheet] 0.65 1080p MVSP Type A DMD
	DLP9000XUV	2Mb / 57P	[Old version datasheet] DLP9000XUV 0.9 UV WQXGA Type A DMD
Agilent(Hewlett-Packard...	MR-0120.008	116Kb / 2P	DMD MASTR
Texas Instruments	DLP3010	687Kb / 39P	[Old version datasheet] DMD
	DLP6500FYE	761Kb / 51P	[Old version datasheet] DMD
	DLP4710	821Kb / 39P	[Old version datasheet] DMD

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