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DLPC150ZEZ Datasheet(PDF) 5 Page - Texas Instruments |
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DLPC150ZEZ Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 55 page  DLPC150 www.ti.com DLPS048B – MARCH 2015 – REVISED OCTOBER 2015 Pin Functions (continued) PIN I/O(1) DESCRIPTION NAME NO. Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal will cause the DLPC150 to PARK the DMD, but it will not power down the PROJ_ON G14 B1 DMD (the DLPA2000 or DLPA2005 controls the power down). The minimum high time is 200 ms. The minimum low time is also 200 ms. Host interrupt (output) This signal has two primary uses. The first use is to indicate when DLPC150 auto-initialization is in progress and most importantly when it completes. The second is to indicate when service is HOST_IRQ(2) N8 O9 requested (that is an interrupt request). The DLPC150 tri-states this output during reset and requires an external pullup to drive this signal to its inactive state. I2C slave (port 0) SCL A bidirectional, open-drain signal with input hysteresis that requires an external pullup. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by IIC0_SCL N10 B7 VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers). I2C slave (port 0) SDA. A bidirectional, open-drain signal with input hysteresis that requires an external pullup. The slave I2C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by IIC0_SDA N9 B7 VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I2C input buffers). PARALLEL PORT INPUT DATA AND CONTROL PCLK P3 I11 Pixel clock(3) PDM_CVS_TE N4 B5 Parallel data mask(4) VSYNC_WE P1 I11 Vsync(5) HSYNC_CS N5 I11 Hsync(5) Data valid active high framing signal.(5) DLPC150 also offers a manual data framing mode through DATAEN_CMD P2 I11 a software command. Refer to the DLPC150 Programmer's Guide for more information on the manual data framing command. (TYPICAL RGB 888) PDATA_0 K2 Blue (bit weight 1) PDATA_1 K1 Blue (bit weight 2) PDATA_2 L2 Blue (bit weight 4) PDATA_3 L1 Blue (bit weight 8) I11 PDATA_4 M2 Blue (bit weight 16) PDATA_5 M1 Blue (bit weight 32) PDATA_6 N2 Blue (bit weight 64) PDATA_7 N1 Blue (bit weight 128) (TYPICAL RGB 888) PDATA_8 R1 Green (bit weight 1) PDATA_9 R2 Green (bit weight 2) PDATA_10 R3 Green (bit weight 4) PDATA_11 P4 Green (bit weight 8) I11 PDATA_12 R4 Green (bit weight 16) PDATA_13 P5 Green (bit weight 32) PDATA_14 R5 Green (bit weight 64) PDATA_15 P6 Green (bit weight 128) (2) For more information about usage, see Host_irq Usage Model. (3) Pixel clock capture edge is software programmable. (4) The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to ground through an external resistor (8 k Ω or less). (5) VSYNC, HSYNC, and DATAEN polarity is software programmable. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DLPC150 |
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