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DLPC900ZPC Datasheet(PDF) 6 Page - Texas Instruments |
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DLPC900ZPC Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 72 page  DLPC900 DLPS037A – OCTOBER 2014 – REVISED AUGUST 2015 www.ti.com DMD Control Pin Functions PIN I/O I/O TYPE CLK SYSTEM DESCRIPTION (1) POWER NAME NUMBER DMD output-enable (active low). This signal does not apply to the slave controller in a two-controller system configuration. DADOEZ AE7 VDD33 O5 Async On the slave controller, this pin is reserved and should be left unconnected. DADADDR_3 AD6 DMD address. This signal does not apply to the slave DADADDR_2 AE5 controller in a two-controller system configuration. On the VDD33 O5 Async DADADDR_1 AF4 slave controller, this pin is reserved and should be left DADADDR_0 AB8 unconnected. DMD mode. This signal does not apply to the slave controller DADMODE_1 AD7 in a two-controller system configuration. On the slave VDD33 O5 Async DADMODE_0 AE6 controller, this pin is reserved and should be left unconnected. DMD select. This signal does not apply to the slave controller DADSEL_1 AE4 in a two-controller system configuration. On the slave VDD33 O5 Async DADSEL_0 AC7 controller, this pin is reserved and should be left unconnected. DMD strobe. This signal does not apply to the slave controller in a two-controller system configuration. On the slave DADSTRB AF5 VDD33 O5 Async controller, this pin is reserved and should be left unconnected. I4 DMD interrupt (active low). Requires an external 1-k Ω pullup DAD_INTZ AC8 VDD33 Async H resistor. (1) Refer to the Typical Single Controller Chipset and the Typical Two Controller Chipset for a description between a one controller and a two controller configuration. 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: DLPC900 |
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