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DLPC3430CZVBR Datasheet(PDF) 7 Page - Texas Instruments |
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DLPC3430CZVBR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 59 page  7 DLPC3430, DLPC3435 www.ti.com DLPS038B – JULY 2014 – REVISED FEBRUARY 2016 Product Folder Links: DLPC3430 DLPC3435 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Pin Functions – DMD Reset and Bias Control PIN I/O DESCRIPTION NAME NUMBER DMD_DEN_ARSTZ B1 O2 DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is supplied, this signal will be driven low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the DLPC343x is independent of the 1.8-V power to the DMD, then TI recommends a weak, external pulldown resistor to hold the signal low in the event DLPC343x power is inactive while DMD power is applied. DMD_LS_CLK A1 O3 DMD, low speed interface clock DMD_LS_WDATA A2 O3 DMD, low speed serial write data DMD_LS_RDATA B2 I6 DMD, low speed serial read data Pin Functions – DMD Sub-LVDS Interface PIN I/O DESCRIPTION NAME NUMBER DMD_HS_CLK_P DMD_HS_CLK_N A7 B7 O4 DMD high speed interface DMD_HS_WDATA_H_P DMD_HS_WDATA_H_N DMD_HS_WDATA_G_P DMD_HS_WDATA_G_N DMD_HS_WDATA_F_P DMD_HS_WDATA_F_N DMD_HS_WDATA_E_P DMD_HS_WDATA_E_N DMD_HS_WDATA_D_P DMD_HS_WDATA_D_N DMD_HS_WDATA_C_P DMD_HS_WDATA_C_N DMD_HS_WDATA_B_P DMD_HS_WDATA_B_N DMD_HS_WDATA_A_P DMD_HS_WDATA_A_N A3 B3 A4 B4 A5 B5 A6 B6 A8 B8 A9 B9 A10 B10 A11 B11 O4 DMD high speed interface lanes, write data bits: (The true numbering and application of the DMD_HS_DATA pins are software configuration dependent) |
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