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TS3005 Datasheet(PDF) 8 Page - Silicon Laboratories |
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TS3005 Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 12 page TS3005 Page 8 TS3005 Rev. 1.0 THEORY OF OPERATION The TS3005 is a user-programmable oscillator where the period of the square wave at its FOUT terminal is generated by an external resistor connected to the RSET pin. The output period is given by: tFOUT (s) = 8 FDIV2:0 x RSET x 512 1.08E11 Equation 1. FOUT Frequency Calculation where FDIV2:0 = 0 to 7 With an RSET = 4.32M Ω and FDIV2:0=111, the FOUT period is approximately 715.88 minutes with a 50% duty cycle. As design aids, Tables 2 lists TS3004’s typical FOUT period for various standard values for RSET and FDIV2:0 = 111(7). The output period can be user-adjusted from 1.7ms to 33hrs without additional components. Frequency divider inputs FDIV2:0 can be set to a logic state HIGH or LOW in order to set the desired frequency as shown in to Table 1. The TS3005 also provides a separate PWM output signal at its PWMOUT terminal that is anti-phase with respect to FOUT. A dead time of approximately 106ns exists between FOUT and PWMOUT. To adjust the pulse width of the PWMOUT output, a single capacitor can be placed at the CPWM pin. To determine the capacitance needed for a desired pulse width, the following equation is to be used: CPWM(F)= Pulse Width(s) x ICPWM VCPWM≅300mV Equation 2. CPWM Capacitor Calculation where ICPWM and VCPWM is the current supplied and voltage applied to the CPWM capacitor, respectively. The pulse width is determined based on the period of FOUT and should never be greater than the period at FOUT. Make sure the PWM_CNTRL pin is set to at least 400mV when calculating the pulse width of PWMOUT. Note VCPWM is approximately 300mV, which is the RSET voltage. Also note that ICPWM is either 1µA or 100nA. Refer to Table 1. The PWMOUT output pulse width can be adjusted further after selecting a CPWM capacitor This can be achieved by applying a voltage to the PWM_CNTRL pin between VRSET and GND. With a voltage of at least VRSET, the pulse width is set based on Equation 2. For example, with a period of 20.5ms( 49Hz) a 10nF capacitor at the CPWM pin generates a pulse width of approximately 3ms. This can be calculated using equation 2. By reducing the PWM_CNTRL voltage from VRSET ≅ 300mV to GND, the pulse width can be reduced further. Note that as the FOUT frequency increases, the amount of pulse width reduction reduces and vice versa. Furthermore, if the PWMOUT output is half the frequency of the FOUT output, this means your CPWM capacitor is too large and as a result, the pulse width is greater than the FOUT period. In this case, use Equation 2 and reduce the capacitor value to less than the period. Connect CPWM to VDD to disable the PWM function and in turn, save power. Connect PWM_CNTRL to VDD for a fixed PWMOUT output pulse width, which is determined by the CPWM pin capacitor only. APPLICATIONS INFORMATION Minimizing Power Consumption To keep the TS3005’s power consumption low, resistive loads at the FOUT and PWMOUT terminals increase dc power consumption and therefore should be as large as possible. Capacitive loads at the FOUT and PWMOUT terminals increase the TS3005’s transient power consumption and, as well, should be as small as possible. One challenge to minimizing the TS3005’s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. Most instruments exhibit an input capacitance of 15pF or more. Unless buffered, the increase in transient load current can be as much as 400nA. To minimize capacitive loading, the technique shown RSET (M Ω)tFOUT 0.360 59.67min 1 1.09hrs 2.49 6.87hrs 4.32 11.93hrs 6.81 18.81hrs 9.76 26.93hrs 12 33.1hrs Table 2: tFOUT vs RSET for FDIV2:0 = 111(7) Figure 1: Using an External Capacitor in Series with Probes Reduces Effective Capacitive Load. CEXT = 1 1 CLOAD(EFF) - 1 CPROBE Equation 3:External Capacitor Calculation |
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